Equipment having a noise elimination function according to embodiments includes a signal generator configured to generate a signal in which a noise component other than thermal noise is discretely included, a noise detecting unit configured to detect the noise component other than the thermal noise discretely included in output of the signal generator, and a signal correcting unit configured to eliminate the noise component detected by the noise detecting unit from the output of the signal generator, and generation of noise other than thermal noise is detected, and a signal from which noise is reliably eliminated is generated.

A phase correcting device of an embodiment includes a local oscillator that includes an all digital phase-locked loop configured to generate a plurality of kinds of local oscillation signals based on a reference clock, and is configured to give one of the local oscillation signals to a device configured to detect a phase of an inputted signal, a phase detector configured to acquire and output, at a predetermined timing, an output of a phase integrator included in the all digital phase-locked loop, and a phase calculator configured to acquire, a plurality of times at predetermined timings, values outputted from the phase detector and correct the phase of the inputted signal by using a difference between the values.

A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.

Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again.

Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation.

There is provided a phase synchronization circuit including: a generation circuit to which an input clock signal is input, and configured to shift the input clock signal by intervals at which numbers of clocks of the input clock signal become equal so as to generate a plurality of pulse signals; a plurality of counter circuits each configured to measure pulse intervals of each of the plurality of pulse signals generated by the generation circuit, respectively; an average value calculation circuit configured to calculate an average value of measured values by the plurality of counter circuits; a frequency calculation circuit configured to calculate a frequency of the input clock signal from the average value calculated by the average value calculation circuit; and a phase locked loop (PLL) circuit configured to perform a phase synchronization processing on the input clock signal, based on the frequency calculated by the frequency calculation circuit.

Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.

Equipment having a noise elimination function according to embodiments includes a signal generator configured to generate a signal in which a noise component other than thermal noise is discretely included, a noise detecting unit configured to detect the noise component other than the thermal noise discretely included in output of the signal generator, and a signal correcting unit configured to eliminate the noise component detected by the noise detecting unit from the output of the signal generator, and generation of noise other than thermal noise is detected, and a signal from which noise is reliably eliminated is generated.

A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.