According to one embodiment, in a semiconductor integrated circuit, a determination circuit is configured to generate first transition information, second transition information and phase determination information, with respect to a signal level of a modulation signal. The first transition information indicates a state of a first transition edge of transition between a first signal level and a second signal level. The second transition information indicates a state of a second transition edge of transition between a third signal level and a fourth signal level. The phase determination information indicates a result of a phase determination of a clock signal. An estimation circuit is configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.

According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.

A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.

Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.

A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.

Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a counter whose output sequence changes only one bit per counted controlled oscillator output cycle, such as a Gray counter. It further includes a register or latches, which sample(s) the counter output value upon receiving a reference clock pulse. The latches output value represents the measured phase. A binary encoder, such as a Gray-to-binary converter, may translate the measured phase to a binary number. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.