A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.

This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe generating a compensation current based on a number of edges of pulses propagating through a variable delay line including multiple delay elements. The number of edges propagating through the variable delay is determined by computing a difference between a number of edges entering the variable delay line and a number of edges exiting the variable delay line. The compensation current is derived from a mirrored version of the current of the control signal of the PLL. Thus, the techniques and systems in this disclosure provide accurate and repeatable control of a variable delay line over variations in temperature and process using low-power circuits. Furthermore, the input signal to the variable delay line may be asynchronous with respect to a system clock or a reference signal of the PLL.

The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator. A variation correction unit generates the control signal FREQ_CTRL on the basis of the variation detected by the variation detection unit, and corrects the variation of the oscillation frequency caused by the interference accompanied by the amplifying operation of the power amplifier.

A device and method is presented to allow the high frequency clock generators and functional blocks of a wireless communication device to enter a very low power sleep state while the low frequency reference clock generator within the wireless communications device remains in an active state. The timing block provides methods of increasing and maintaining accuracy of the system timer which may have been reduced by temperature variation or manufacturing defects. The timing block also allows for selection of the highest accuracy clock from among multiple high frequency clock references. A device for timing control is presented comprising at least one high frequency reference clock, a low frequency reference clock and a timing controller for generating a system timer, wherein the timing controller selects one of the at least one high frequency reference clock and processes the low frequency reference clock with the selected high frequency reference clock.

A phase controller for an antenna array includes a determination circuit, determining a direction index of the antenna array, and calculating a phase index according to the direction index according to a congruence modulo equation; a switching box, selecting L first frequency signals with L different first phases among K first frequency signals with K different first phases according to the phase index, wherein L and K are integer larger than 1, and L is not larger than K; and a frequency synthesizing module, comprising L phase-coherent PLL frequency synthesizers for receiving the L first frequency signals with the L different first phases to generate L second frequency signals with L different second phases to L antennae of the antenna array, wherein a second frequency of the second frequency signals is larger than a first frequency of the first frequency signals.

An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.

An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

A method of producing a low spurious output signal in a frequency generator circuit comprises, in a direct digital synthesizer (DDS), generating a signal at a first frequency; mixing the signal to produce a signal at a second frequency in an operating band of interest higher than the first frequency; determining spurious signals in the second frequency signal due to non-linearity in a digital to analog converter (DAC) of the DDS; generating at least one amplitude and frequency vector containing information relating to an amplitude value and frequency value representative of one of the determined spurious energy signals; generating a pre-distortion signal based on the at least one amplitude and frequency vector; and combining the pre-distortion signal with the signal generated by the DDS to produce a corrected output signal, wherein the pre-distortion signal is phase offset from a corresponding determined spurious signal to cancel the corresponding determined spurious signal.

This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe generating a compensation current based on a number of edges of pulses propagating through a variable delay line including multiple delay elements. The number of edges propagating through the variable delay is determined by computing a difference between a number of edges entering the variable delay line and a number of edges exiting the variable delay line. The compensation current is derived from a mirrored version of the current of the control signal of the PLL. Thus, the techniques and systems in this disclosure provide accurate and repeatable control of a variable delay line over variations in temperature and process using low-power circuits. Furthermore, the input signal to the variable delay line may be asynchronous with respect to a system clock or a reference signal of the PLL.