A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. Further, the method includes determining information on the phase continuity using the at least one sample.

A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.

A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.

An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.

An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.

Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.

An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.

An auto trimming device includes an oscillator configured to generate an oscillator clock signal, a subtractor configured to receive an expected value for a target frequency and the oscillator clock signal, configured to output a difference value between the expected value and the oscillator clock signal, an index value selector configured to calculate a unit index value using the difference value and configured to detect and output a target index value from the unit index value, an index value register configured to output an oscillator trimming code corresponding to the target index value to the oscillator, and an embedded memory configured to store the oscillator trimming code as a target oscillator trimming code for the target frequency.