Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F.sub.S/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

An oscillator includes: an outer package; an inner package accommodated in the outer package and fixed to the outer package via a heat insulating member; a vibration element accommodated in the inner package; a temperature sensor; a first circuit element accommodated in the inner package and including an oscillation circuit configured to oscillate the vibration element and generate a temperature-compensated oscillation signal based on the temperature sensor; and a second circuit element fixed to the outer package and including a frequency control circuit configured to control a frequency of the oscillation signal.

A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.

Embodiments of this application disclose a wireless transceiver apparatus. The apparatus includes a radio frequency receiver, a radio frequency transmitter, a first serializer/deserializer, and a common clock phase-locked loop. The radio frequency receiver, the radio frequency transmitter, the first serializer/deserializer, and the common clock phase-locked loop are integrated in a radio frequency chip. The radio frequency receiver includes a down converter and an analog to digital converter. The radio frequency transmitter includes an up converter and a digital to analog converter. The first serializer/deserializer is configured to provide a serial digital interface with a baseband chip for the radio frequency chip. Coupled to the analog to digital converter, the digital to analog converter, and the first serializer/deserializer separately, the common clock phase-locked loop is configured to provide a clock signal for the analog to digital converter, the digital to analog converter, and the first serializer/deserializer.

Provided are a differential signal skew calibration circuit and a semiconductor memory. The differential signal skew calibration circuit may acquire a phase relationship of a differential signals through a phase detection circuit. A phase adjustment control circuit may generate a phase calibration control instruction according to the phase relationship of the differential signals to control a phase calibration circuit to calibrate a phase skew of the input differential signals.

Provided are a differential signal skew calibration circuit and a semiconductor memory. The differential signal skew calibration circuit may acquire a phase relationship of a differential signals through a phase detection circuit. A phase adjustment control circuit may generate a phase calibration control instruction according to the phase relationship of the differential signals to control a phase calibration circuit to calibrate a phase skew of the input differential signals.

A technology related to an electronic circuit, specifically, a phase locked loop or a frequency synthesizing apparatus, is disclosed. The frequency synthesizing apparatus includes an injection locked frequency divider and a replica frequency divider having the same circuit configuration as the injection locked frequency divider. A control value required for self-oscillating at a target frequency using the replica frequency divider is determined. When the injection locked frequency divider fails injection locking on a first attempt, the injection locking may be attempted using the determined control value. On the first attempt, the control value of the injection locked frequency divider may be determined and stored in advance according to a temperature and a supply voltage.

In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

A frequency divider functionality detection and adjustment circuit includes an auxiliary voltage controlled oscillator (VCO) coupled to a first multiplexer (MUX), a programmable divider coupled to the first MUX, a second MUX coupled to the programmable divider, a counter coupled to the second MUX, and a controller coupled to the counter, the controller configured to adjust a supply voltage provided to the programmable divider based on a measured divide ratio, NMEAS.

An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.