An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

Described herein is a method and apparatus for a multi-beam digital system including a frequency reference device having an output for providing a frequency reference signal; a fanout device connected to the frequency reference device and configured to generate n frequency reference signals from the frequency reference signal output from the frequency reference device, having n outputs configured to output the n frequency reference signals, respectively, where n is a positive integer; n local clock domain devices configured to synchronize the n frequency reference signals and distribute reference and clock signals having deterministic phase and phase/data alignment; and n beamforming devices connected to the n local clock domain devices, respectively, and configured to form a user-definable beam, and having n input configured to receive n radio frequency (RF) signals, and n outputs for transmitting n RF signals.

A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

An electronic circuit includes a first pin corresponding to a reference signal and a second pin corresponding to an external resistor, the external resistor being connected on a first side to the second pin and connected on a second side to ground. The apparatus also includes a first oscillator having a first frequency loop configured to: receive, via the first pin, the reference signal; receive, via the second pin, a current associated with voltage applied to the external resistor; and lock a first frequency output at a frequency associated with the reference signal. The apparatus also includes a second oscillator having a second frequency loop configured to: receive the first frequency output; scale the frequency of the first frequency output; and lock a second frequency output at the scaled frequency of the first frequency output.

A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (ϕ.sub.adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (f.sub.osc1, f.sub.osc2) based on an adjustment signal applied to the adjustment input (ϕ.sub.adj).

A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (ϕ.sub.adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (f.sub.osc1, f.sub.osc2) based on an adjustment signal applied to the adjustment input (ϕ.sub.adj).

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.

A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.