A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

An analog-to-digital converting circuit includes: an analog-to-digital converter suitable for performing an analog-to-digital conversion on pixel signals of a plurality of pixels provided in a pixel array; a ramp signal generator suitable for providing a ramp signal to the analog-to-digital converter; and an auto-zero controller suitable for providing a reference voltage to the analog-to-digital converter to perform an auto-zeroing operation by using a row pixel for which a readout operation is performed by the analog-to-digital converter.

A disclosed comparator includes a comparison circuit including a differential unit that compares an input signal with a reference signal and changes a level of a signal output to a first node in accordance with a result of comparison and an amplifier unit that includes a load element and outputs a signal in accordance with a potential of the first node to a second node, and a positive feedback circuit that is connected to the second node and a third node and changes a level of a signal at the third node at a rate higher than a change rate of a level of a signal at the second node in accordance with a change in a level of a signal at the second node.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.

One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.

An analog-to-digital converter circuit includes: a first operation amplifier suitable for comparing a ramp voltage and a voltage to be converted so as to produce an amplification result and outputting the amplification result; a second operation amplifier suitable for comparing the amplification result transferred to a first input terminal with a reference voltage transferred to a second input terminal so as to produce a comparison result and outputting the comparison result; a leakage current measurer suitable for measuring a leakage current to the first input terminal; and a leakage current generator suitable for causing a current of the same amount as that of the leakage current measured by the leakage current measurer to flow to the second input terminal.