A signal receiver divides frequency conversion into multiple steps based on a Log.sub.2(N) number corresponding to the number N of Nyquist zones that are to be covered. This binary structure used Track and Hold (T/H) amplifiers as samplers for wideband frequency conversion where the frequency coverage is defined by a number of cascaded segments. The receiver system includes a plurality of conversion stages coupled in series with one another. Each conversion stage includes a bandpass filter at its input node with a T/H amplifier configured to receive a respective T/H clock signal. Each conversion stage is either bypassed or implemented depending on the frequency bandwidth being processed. Each bandpass filter is configured to have a respective bandwidth range that differs from the bandwidth range of the other bandpass filters. Each T/H amplifier is configured to receive a respective T/H clock input signal.

An array-based Compressed sensing Receiver Architecture (ACRA) includes an antenna array with two or more antennas connected to two or more ADCs that are clocked at two or more different sampling rates below the Nyquist rate of the incident signals. Comparison of the individual aliased outputs of the ADCs allows for estimation of signal component characteristics, including signal bandwidth, center frequency, and direction-of-arrival (DoA). Multiple digital signal processing (DSP) techniques, such as sparse fast Fourier transform (sFFT), can be employed depending on the type of detection or estimation.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CT achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS/s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.

A system comprises an analog front end (AFE), an analog-to-digital converter (ADC), and alias detection circuitry. The AFE may be operable to receive an analog signal via a communication medium, wherein a first frequency band of the analog signal is occupied by an OFDM symbol and a second frequency band of the analog signal is occupied by first aliases generated during digital-to-analog conversion of the OFDM symbol. The ADC is operable to digitize the particular band of the analog signal to generate a digital signal, wherein, during the digitization, aliasing of the first aliases results in second aliases which fall into the first frequency band. The alias detection circuitry is operable to detect the second aliases in the first frequency band of the digital signal, and process the digital signal based on the detected second aliases to generate an output signal.

A system comprises an analog front end (AFE), an analog-to-digital converter (ADC), and alias detection circuitry. The AFE may be operable to receive an analog signal via a communication medium, wherein a first frequency band of the analog signal is occupied by an OFDM symbol and a second frequency band of the analog signal is occupied by first aliases generated during digital-to-analog conversion of the OFDM symbol. The ADC is operable to digitize the particular band of the analog signal to generate a digital signal, wherein, during the digitization, aliasing of the first aliases results in second aliases which fall into the first frequency band. The alias detection circuitry is operable to detect the second aliases in the first frequency band of the digital signal, and process the digital signal based on the detected second aliases to generate an output signal.

A signal monitoring system includes a splitter circuit, a single-bit channel circuit, a multi-bit channel circuit, and a frequency processor circuit. The splitter circuit splits a first analog signal into second and third analog signals. The single-bit channel circuit samples the second analog signal at a sampling rate that is greater than or equal to a Nyquist rate of the second analog signal to generate a first digital signal. The multi-bit channel circuit under-samples the third analog signal at a sampling rate that is less than a Nyquist rate of the third analog signal to generate second digital signals. The frequency processor circuit resolves a Nyquist zone ambiguity in the second digital signals using the first digital signal to generate an unambiguous output signal.

A detection device includes a driving circuit and a detection circuit. The detection circuit includes first and second electric charge-voltage conversion circuits to which first and second detection signals are input, first and second gain adjustment amplifiers that amplify output signals of the circuits, a switching mixer that has first and second input nodes to which the output signals of the first and second gain adjustment amplifiers are input, and performs differential synchronous detection thereon on the basis of a synchronization signal from the driving circuit, so as to output first and second output signals to first and second output nodes, first and second filters that receive the first and second output signals from the first and second output nodes of the switching mixer, and an A/D conversion circuit that receives output signals from the first and second filters so as to perform differential A/D conversion thereon.

An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CT achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS/s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.