An analog or digital to encoder signal converter is provided that includes a current sense circuit, if an analog input, configured to receive an analog signal from a sensor and convert the signal into a digital signal via an analog-to-digital converter. The digital signal is processed to generate an appropriate reading value and an encoder string is made that represents the desired value for data transmission, wherein the string is formatted for a selected, specific encoder reader protocol. In this way, existing data collection systems that require a specific encoder protocol for data transmissions can be expanded to collect data from any sensing device with an analog or digital output, thereby adding value to existing encoder data collection systems by enabling them to collect data from devices other than just the customer billing meters for which the encoder protocol networks were designed.

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.

An analog or digital to encoder signal converter is provided that includes a current sense circuit, if an analog input, configured to receive an analog signal from a sensor and convert the signal into a digital signal via an analog-to-digital converter. The digital signal is processed to generate an appropriate reading value and an encoder string is made that represents the desired value for data transmission, wherein the string is formatted for a selected, specific encoder reader protocol. In this way, existing data collection systems that require a specific encoder protocol for data transmissions can be expanded to collect data from any sensing device with an analog or digital output, thereby adding value to existing encoder data collection systems by enabling them to collect data from devices other than just the customer billing meters for which the encoder protocol networks were designed.

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Techniques are provided for compacting indirect blocks. For example, an object is represented as a structure including data blocks within which data of the object is stored and indirect blocks including block numbers of where the data blocks are located in storage. Block numbers within a set of indirect blocks are compacted into a compacted indirect block including a base block number, a count of additional block numbers after the base block number in the compacted indirect block, and a pattern of the block numbers in the compacted indirect block. The compacted indirect block is stored into memory for processing access operations to the object. Storing compacted indirect blocks into memory allows for more block numbers to be stored within memory.

An analog-to-digital converter includes a comparator configured to compare an input voltage and a conversion voltage and to generate a comparison result; a digital-to-analog converter configured to generate the conversion voltage according to a digital output signal; and a control circuit including a conversion control circuit configured to determine the digital output signal corresponding to the input voltage based on the comparison result; and a correction control circuit configured to correct an error of the digital output signal by increasing or decreasing the digital output signal based on the comparison result after the digital output signal is determined.