A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.

The present disclosure relates to an imaging element and a method for controlling an imaging element, an imaging apparatus, and an electronic apparatus that can reduce the size of the imaging element and can reduce power consumption. First, a gray code corresponding to a P-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and a binary code of the pixel signal in which all bits are 0 and which is latched in a temporary latch is continuously calculated and is latched as the binary code of the P-phase pixel signal in the temporary latch. Then, a gray code corresponding to a D-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and the binary code of P-phase the pixel signal which is latched in the temporary latch is continuously calculated. The present disclosure can be applied to an imaging apparatus.

An electronic device includes a digital-to-analog converter coupled to receive a reference voltage and a binary-encoded digital input signal. The electronic device provides an analog output signal that represents the value of the binary-encoded digital input signal and a transmission gate is coupled to pass the analog output signal. A blank pulse generator is coupled to receive selected bits of the binary-encoded digital input signal and to pulse the transmission gate off when the selected bits change value, thus providing a blanked analog output signal.

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

An electronic device includes a digital-to-analog converter coupled to receive a reference voltage and a binary-encoded digital input signal. The electronic device provides an analog output signal that represents the value of the binary-encoded digital input signal and a transmission gate is coupled to pass the analog output signal. A blank pulse generator is coupled to receive selected bits of the binary-encoded digital input signal and to pulse the transmission gate off when the selected bits change value, thus providing a blanked analog output signal.

A latch circuit includes a switch circuit, an input circuit, and an output circuit. The switch circuit is coupled between a first power node and a second power node, and includes a non-inverting output node and an inverting output node. The input circuit couples with the non-inverting output node and the inverting output node, and conducts the non-inverting output node with the second power node according to a clock signal and a data signal. The output circuit couples with the non-inverting output node, the inverting output node, the first power node, and the second power node. The output circuit conducts the non-inverting output node with the first power node according to the clock signal and the data signal. When the data signal is switched, the switch circuit sets a conductive path from the first power node to the second power node as an open circuit.

In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.

The present disclosure relates to an imaging element and a method for controlling an imaging element, an imaging apparatus, and an electronic apparatus that can reduce the size of the imaging element and can reduce power consumption. First, a gray code corresponding to a P-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and a binary code of the pixel signal in which all bits are 0 and which is latched in a temporary latch is continuously calculated and is latched as the binary code of the P-phase pixel signal in the temporary latch. Then, a gray code corresponding to a D-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and the binary code of P-phase the pixel signal which is latched in the temporary latch is continuously calculated. The present disclosure can be applied to an imaging apparatus.

Clock alignment circuitry may include phase detection circuitry and programmable delay circuitry to facilitate aligning a data signal with a particular state of a clock signal. For example, phase detection circuitry may be disposed at a location of interest to monitor the relative timing of the clock signal and the data signal. Based on the monitored states, the programmable delay circuitry may determine the delay to be applied to the data signal (e.g., prior to propagating through logic operations and transmission to the location of interest) such that the data signal later arrives at the location of interest at a suitable time. Effectively, a programmable delay is added to the delay encountered by the data signal during processing and transmission to the location of interest such that the total delay results in the data signal arriving at the location of interest while the clock signal is in the desired state.