A digital technique to reduce or minimize switching in a DAC by using a partial DAC data ignore switching mode. In the partial DAC data ignore switching mode, a control circuit compares first and second data, such a first and second digital words, and operates corresponding switches only when the first data differ from the second data. The techniques are applicable to many types of DACs, including voltage output DACs, current output DACs, variable resistance DACs, digital rheostats, digital potentiometers, digiPOTs.

To prevent that the noise occurs at timing switching between PCM data and DSD data by a simple configuration.

An AV receiver 1 includes a mute circuit 5 that mutes output from a DAC 4, a detection circuit 6 that detects that a digital audio signal is zero data and supplies a detection signal, a microcomputer 2 that supplies a control signal at timing switching from PCM data to DSD data before switches from PCM mode that the DAC 4 converts PCM data into an analog audio signal to DSD mode that the DAC 4 converts DSD data into the analog audio signal, and an AND circuit 7 that activates the mute circuit 5 in case that the detection signal from the detection circuit 6 and the control signal from the microcomputer 2 are supplied.

A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.