A successive approximation register analog-to-digital converter including a first capacitor group, a second capacitor group and a control circuit is provided. Each of the first and second capacitor groups includes a plurality of capacitors coupled to a common node. In a sampling mode, the control circuit provides an analog signal to the first capacitor group and provides a first voltage to the common node and the second capacitor group. In a sampling mode, the control circuit stops providing the first voltage to the common node and provides a second voltage to the second capacitor group. In a data converting mode, the control circuit reads voltage values of the capacitors of the first capacitor group in sequence. Each when the voltage of at least one specific capacitor in the first capacitor group is read, one capacitor of the second capacitor group is electrically floated.

A device and a method for digital to analog conversion are provided. The device contains a signal generation circuit and a conversion circuit. The signal generation circuit generates two reset signals which are a first reset signal and a second reset signal. The two reset signals are mutually inverted digital signals and contain the same number of bits. The conversion circuit converts a digital data signal into an analog data signal when a first clock signal is at a first level, and generates the analog data signal at two reset levels respectively according to the two reset signals when the first clock signal is at a second level.

An audio device for reducing pop noise is adapted to compensate for a direct current (DC) offset of an audio source signal and output the audio source signal to an audio playing device. The audio device includes a linear operation circuit, an adder, a digital-to-analog circuit, and an amplification circuit. The digital-to-analog circuit is coupled between the adder and the amplification circuit. The linear operation circuit generates a DC offset value based on a linear equation, a temperature parameter, a slope parameter, and a constant. The adder is configured to process an input signal and the DC offset value to generate a calibration signal. The digital-to-analog circuit is configured to convert a calibration signal in a digital form to a calibration signal in an analog form. The amplification circuit is configured to process the calibration signal in the analog form to output the audio source signal.

A successive approximation register analog-to-digital converter including a first capacitor group, a second capacitor group and a control circuit is provided. Each of the first and second capacitor groups includes a plurality of capacitors coupled to a common node. In a sampling mode, the control circuit provides an analog signal to the first capacitor group and provides a first voltage to the common node and the second capacitor group. In a sampling mode, the control circuit stops providing the first voltage to the common node and provides a second voltage to the second capacitor group. In a data converting mode, the control circuit reads voltage values of the capacitors of the first capacitor group in sequence. Each when the voltage of at least one specific capacitor in the first capacitor group is read, one capacitor of the second capacitor group is electrically floated.

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Systems and methods for suppressing transient outputs from an amplifier system are provided. An amplifier having a plurality of bias levels may be controlled to initiate a change in the level of a bias signal provided to the amplifier. The level of the bias signal is ramped from an initial bias level to a final bias level over numerous steps. The steps include at least one step in which the level of the bias signal is between the initial bias level and the final bias level. An amplifier system having multiple stages may be controlled to enable each stage and selectively couple each stage in a sequence that couples an output stage to an output terminal at the completion of the sequence.

An ion movement control apparatus with low pass filter switch , including a digital to analog converter (DAC) connected to a first port and enabled to provide a DAC voltage, an electrode element connected to a second port, the electrode element configured to provide an electrical field for controlling a position of an ion, and a filter switch between the first port and the second port and having a filter leg and a bypass leg in parallel, the filter leg having a filter leg switch and a filter portion between the first port and the second port and selectively coupling the first port through the filter leg to the second port to slow a voltage transient of the DAC voltage to the electrode element, and where the bypass leg has a bypass leg switch that selectively couples the first port directly to the second port.

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.