A method includes sampling an input voltage signal applied to an ADC, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining in a search logic block a digital code representation for the comparison result. The method may also include performing a calibration by: performing an additional cycle, wherein a last comparison carried out for determining a least significant bit of the digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode, so obtaining an additional comparison; determining from a difference between results of the additional comparison and the last comparison a sign of a comparator offset error between the comparator resolution modes; and tuning, in accordance with a sign of the comparator offset error, a programmable capacitor connected at an input of the comparator, thereby inducing a voltage step to counteract the comparator offset error.

An apparatus can include a digital-to-analog converter (DAC) and calibration circuitry including an oscillator. The calibration circuitry can be coupled to an output of the DAC, the calibration circuitry to sample and count DAC output pulses for at least two consecutive pulses using at least two separate counter circuits. The calibration circuitry can determine error between at least two consecutive pulses and provide a correction value based on the error. The apparatus can further include correction circuitry to provide a calibration signal to the DAC based on the correction value.

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

A signal receiving circuit receives an input signal and includes a radio frequency (RF) front-end circuit, a filter circuit, an amplifier circuit, an analog-to-digital converter (ADC), a compensation circuit, an adder circuit, and a control circuit. The RF front-end circuit down-converts the input signal to generate a down-converted signal. The filter circuit filters the down-converted signal to generate a filtered signal. The amplifier circuit amplifies, according to a control signal, the filtered signal with a gain to generate an amplified signal. The ADC converts the amplified signal into a first digital code. The compensation circuit generates a compensation code according to at least one of the control signal and the gain. The adder circuit generates a second digital code according to the compensation code and the first digital code. The control circuit generates the control signal according to the second digital code.

A method may include generating, via a sigma-delta DAC, a series of analog voltage levels that are equally spaced across a selected portion of ADC range; measuring, via the ADC, the series of analog voltages levels generated via the sigma-delta DAC; determining an error of a system at least partially based on a comparison of ADC output values and expected ADC output values, the system including the sigma-delta DAC and the ADC; modeling the error of the system using a combination of piecewise linear basis functions representing different types of errors or offsets; and determining a gain error of the ADC at least partially based on a coefficient of a linear basis function corresponding to the gain error of the ADC, the linear basis function one of the piecewise linear basis functions used to model the error of the system.

A digital microphone includes a first modulation path having an input for receiving an analog input signal and an output for generating a first digital signal; a second modulation path having an input for receiving the analog input signal and an output for generating a second digital signal; a summing circuit having a first input for receiving the first digital signal, a second input for receiving the second digital signal, and an output for generating a digital calibration path signal; and a difference circuit having a first input for receiving the first digital signal, a second input for receiving the second digital signal, and an output for generating a digital signal path signal.