An apparatus configured to convert an analog input signal into a digital output signal may include a first amplification circuit configured to receive the analog input signal and a plurality of reference voltages and amplify differences between the analog input signal and the plurality of reference voltages; a plurality of first capacitors configured to respectively store charges corresponding to signals outputted by the first amplification circuit; a second amplification circuit configured to amplify differences among voltages of the plurality of first capacitors; a plurality of second capacitors configured to respectively store charges corresponding to signals outputted by the second amplification circuit; and a comparison circuit configured to generate the digital output signal by comparing voltages of the plurality of second capacitors with each other.

A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

A control circuit and a method of calibrating a signal converter (such as DAC) are disclosed. The control circuit can be an existing control circuit, so no additional calibration circuit is required and the circuit area can be reduced. The control circuit can be an embedded microcontroller or other type of microcontroller. In general, the microcontroller includes an analog comparator and an arithmetic unit. With the combination of using the arithmetic unit to execute firmware program codes and using of the analog comparator, the control circuit is able to calibrate the signal converter.

The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

An analog-to-digital converter of one embodiment in the present disclosure may comprise a first conversion unit generating an internal clock signal, generating a first digital code and a residual signal by converting an input signal in a successive approximation register (SAR) method in response to the internal clock signal and generating a flash clock signal in response to an external clock signal, a second conversion unit generating a second digital code by converting the residual signal in a flash method in response to the flash clock signal, and an output circuit generating an output digital signal in response to the first digital code and the second digital code.