Systems, apparatuses, and methods for performing hybrid non-linearity correction for a digital-to-analog converter (DAC) are described. A circuit includes two correction LUTs, an edge-trim DAC, and a DAC core. A lookup of a first correction LUT is performed using a portion of the most significant bits (MSBs) of a received digital input value. A first correction value, retrieved from the first correction LUT, is applied to the digital input value to generate a corrected value. The corrected value is provided to the DAC core and to a second correction LUT. A second correction value, retrieved from the second correction LUT, is compared to the first correction value. If the second correction value is different from the first correction value, the difference is provided to the edge-trim DAC to generate an analog correction which is applied to an analog output of the DAC core.

An AD converter is provided with a control unit including a calibration control unit that controls an operation for calibrating the control unit and a conversion control unit that controls an operation for converting a target input voltage into a digital signal; a reference voltage unit that outputs a reference voltage; and an integrating converter unit including an integrating unit that generates an integrated voltage by integrating a predetermined unit voltage, a comparator that has two inputs and compares the integrated voltage and an input voltage or a reference voltage Vref, and a crossbar switch that switches connections between the case where the integrated voltage is inputted to one of the inputs of the comparator and the input voltage or the reference voltage Vref is inputted to the other input and the case where the input voltage or the reference voltage Vref is inputted to one of the inputs of the comparator and the integrated voltage is inputted to the other input.

A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.

Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.

According to an embodiment, a digital microphone includes an analog-to-digital converter (ADC) for receiving an analog input signal; a DC blocker component coupled to the ADC; a digital low pass filter coupled to the DC block component; and a nonlinear compensation component coupled to the digital low pass filter for providing a digital output signal.

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits

The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.