An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.

An FM-CW radar includes a high frequency circuit that receives a reflected wave from a target, and a signal processing unit that converts an analog signal generated by the high frequency circuit into a digital signal and detects at least a distance to the target and velocity of the target. The high frequency circuit includes a VCO that receives a modulation voltage from the signal processing unit and generates a frequency-modulated high frequency signal. The signal processing unit includes an LUT that stores default modulation control data. The signal processing unit calculates frequency information from phase information of output of the VCO, and updates the data stored in the LUT with correction data that is generated by using a result of the calculation.

A successive-approximation-register (SAR) analog-to-digital converter (ADC) is provided in the invention. The SAR ADC includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.

A digital background calibration circuit including a digital random number generator, an analog-to-digital converter (ADC) and a plurality of switches is provided. The digital random number generator is configured to generate a first digital sequence having a plurality of bits. The ADC includes a plurality of sampling capacitors. The switches receive the first digital sequence and are coupled to the sampling capacitors. During a calibration period, the digital random number generator controls the sampling capacitors via the switches to sample the first digital sequence.

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

A self-calibrating Analog-to-Digital Converter (ADC) performs radix error calibration using a Successive-Approximation Register (SAR) to drive test voltages onto lower-significant capacitors. The final SAR code is corrected by performing LSB averaging on LSB averaging capacitors and then accumulated, and the measurement repeated many times to obtain a digital average measurement. An ideal radix or ratio of the measured capacitor's capacitance to a unit capacitance of an LSB capacitor is subtracted from the digital average measurement to obtain a measured error that is stored in a Look-Up Table (LUT) with the ideal radix. Radix error calibration is repeated for other capacitors to populate the LUT. During normal ADC conversion, the SAR code obtained from converting the analog input is applied to addresses the LUT, and all ideal radixes and measured errors for 1 bits in the SAR code are added together to generate an error-corrected digital value.

Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2.sup.N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.

A method for noise suppression and distortion correction of analog-to-digital converters based on deep learning that realizes effect of correcting noise and distortion of analog to digital converters. The method is applied to electronic ADCs or photonic ADCs. It utilizes the learning ability of the deep network to perform system response learning on ADCs which need noise suppression and distortion correction, establishes a computational model in the deep network that can suppress the reconstruction of noises and distorted signals, performs noise suppression and distortion correction on the signals obtained by ADCs, and thereby improves performance of the learned ADCs. The present invention has a very important role in improving the performance of the microwave photon system with high sampling precision of microwave photon radar and optical communication system.

An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.