An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.

The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

A digital optical receiver capable of adaptively correcting the linearity of an analog front end unit is provided. The digital optical receiver comprises: a photoelectric conversion unit that converts an optical signal into an analog electric signal and outputs the analog electric signal; an analog front end unit that converts the analog electric signal obtained from the photoelectric conversion unit into a digital electric signal and outputs the digital electric signal; a linearity correction unit that corrects the linearity of the digital electric signal obtained from the analog front end unit; a demodulation processing unit that demodulates a signal by using, as input, the digital electric signal obtained from the linearity correction unit; and a control unit that provides an offset signal to the analog electric signal outputted by the photoelectric conversion unit, obtains monitor information for the result of the provision of the offset signal, and controls the linearity correction unit so that the linearity correction unit corrects the linearity of the digital electric signal obtained from the analog front end unit on the basis of the monitor information.

An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

The present disclosure relates to a digital-to-analog converter (DAC) linearization system including a DAC, a summing buffer structure, an analog-to-digital converter (ADC), a calculation system, an error look-up table, and an adder. A combination of the DAC, the summing buffer structure, and the ADC sequentially provide first and second ADC output signals, both of which include DAC integral nonlinearity (INL). The calculation system calculates the DAC INL based on the first and second ADC output signals, the error look-up table provides a correction signal mapping to the calculated DAC INL, and the adder provides a calibrated digital input signal to the DAC based on the correction signal. The calibrated digital input signal ensures the DAC to generate an updated output signal with less nonlinearity and improved purity.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes.

Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.

Each realization of an electric circuit design defines a frequency response. For a test lot of the design, frequency responses are measured, each at a stable value of an environment parameter, wherein the totality of the values are distributed over a parameter range. Based on the measurements, a design-specific model is defined that describes a frequency response of the design in dependence of the environment parameter. For a unit in a main lot of realizations of the design, a unit-specific frequency response is measured at a stable value of the environment parameter; the model is fitted to the response, whereby a unit-specific model is obtained; data representing the unit-specific model is stored in association with the unit; and the unit is operated in conjunction with a compensation stage configured to determine a present value of the environment parameter and compensate drift in relation to a parameter-independent reference frequency response.