Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to pre-cancel an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.

A method for operating an ADC includes storing a sampled input charge on a capacitance of a sample-and-hold circuit including a DAC. The sampled input charge is stored using a first reference signal coupled to the DAC and a second signal. The sampled input charge has a value based on a first digital code. The method includes converting a second digital code to an analog signal on the first node using the DAC, the sampled input charge, and the first reference signal. The second digital code is one least-significant bit different from the first digital code. The method includes generating a monotonicity indicator indicating whether an output analog signal of the DAC is monotonic in response to a transition of a digital input of the DAC from the first digital code to the second digital code based on a comparison of the analog signal to the second signal.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

A DAC current steering circuit includes a first transistor whose: drain is coupled to a first output, source is coupled to a drain of a second transistor at a first node, and gate is coupled to a data input, and a third transistor whose: drain is coupled to a second output, source is coupled to a drain of a fourth transistor at a second node, and gate is coupled to a complement of the data input. The circuit further includes first and second shadow capacitors respectively coupled, via first and second switches, between the first and second nodes and ground, the first and second switches respectively controlled by the complement of the data input, and the data input.

The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2.sup.N1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

A circuit includes a phase control logic, an analog-to-digital converter (ADC), and digital logic. The phase control logic is configured to couple to a plurality of power phases of a multi-phase power supply. The digital logic is configured to couple to the phase control logic and the ADC, to receive an instruction to operate in a self-calibration mode of operation, receive a first message including a value associated with a calibrated load configured to couple to the plurality of power phases, perform a self-calibration sub-routine for each power phase of the plurality of power phases based at least partially on the received instruction, the received first message, and a signal received from the ADC, and receive a second message instructing the digital logic to store a result of the self-calibration in a memory of the circuit.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2.sup.N1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.

Various background calibration techniques to calibrate inter-stage gain, e.g., in pipelined ADCs, are described to allow open loop amplifier circuits to be used as residue amplifiers for better power efficiency. Using various techniques, a well-controlled perturbation can be injected between two conversions and the actual perturbation after a residue amplifier can be measured. By comparing the actual measurement against an expected value, the gain information of the residue amplifier can be estimated and then calibration can be applied.