A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M1 sampling phases of the M sampling phases. The phase control circuit comprises M1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.

In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.

An apparatus for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator. The differential integrator output is chargeable to a threshold prior to an integration period. The differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold. The comparator detects the output of the differential integrator reaching zero. The apparatus includes a closed-loop gain trim circuit to perform a coarse calibration to adjust and set the gain of the differential integrator and a reference generator that generates the threshold to which the differential integrator output is pre-charged. The reference generator is trimmable during a fine calibration to adjust and set the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

A matrix multiplication and addition (MAC) operating system is described where different cell currents flowing through different cells in a matrix for different PWM time intervals can be integrated and converted into a numeric value for the cumulative charge. The numeric value of the cumulative charge computed by the ADC is equivalent to MAC operations over multiplicity of cells. The operation is inherently error prone due to parasitic coupling effects from the switching of the memory cells in the array. The presented system minimizes the errors due to parasitic coupling through memory array.

Certain aspects of the present disclosure provide methods and apparatus for performing background noise estimation using a circular histogram noise figure (CHNF) in an analog-to-digital converter (ADC) circuit with redundancy. The estimated noise may be used to reduce the noise (e.g., comparator noise) in the ADC circuit. One example ADC circuit generally includes at least one of a comparator or a digital-to-analog converter (DAC) and at least one digital feedback input. The at least one digital feedback input is coupled to the at least one of the comparator or the DAC and is configured to adjust at least one parameter of the at least one of the comparator or the DAC based on at least a portion of an output of the ADC circuit.

A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.

A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).

A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Z.sub.i) in the control word (z[n]) has a corresponding bit weight (w.sub.i) and is in the following considered to adopt values in {?1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Z.sub.i) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Z.sub.i) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample. The method comprises, during a measurement procedure, for a first set of at least one bit of the control word (z[n]), generating (300) the bits of the first set, such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero. Furthermore, the method comprises, during the measurement procedure, for a second set of at least one bit of the control word (z[n]), generating (310) the bits of the second set, such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero. The method also comprises detecting (330) a DC level at the output of the DAC during the measurement procedure. The method further comprises adjusting (340) at least one analog weight in response to the detected DC level. A corresponding DAC, a corresponding electronic apparatus, and a corresponding integrated circuit are also disclosed.