For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

During a period of calibration of the ADC, the effect of unexpected external noise can be excluded.

Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.

A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.

During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

A source driver including: a current source that provides an approximately constant current; a channel coupled to a source electrode and including a digital to analog converters (DAC), the DAC including: a voltage source that applies an output voltage to the source electrode based on the approximately constant current provided by the current source; and a control unit having circuitry that: inputs a digital value; and terminates, based on the digital value, charging of the voltage source by the approximately constant current; and a calibration unit having circuitry that: generates a comparison between a test voltage applied by the voltage source with a target voltage; and modifies the approximately constant current based on the comparison.

A sampling assembly and a sampling method are provided. A self-calibration unit controls a first switch to be turned on, to enable a first sampling signal to be input to a sampling unit. The sampling unit processes the first sampling signal to obtain a second sampling signal, and outputs the second sampling signal to the self-calibration unit. The self-calibration unit controls the first switch to be turned off, controls a second switch to be turned on, and outputs a first calibration signal to the sampling unit. The sampling unit processes the first calibration signal to obtain a second calibration signal, and outputs the second calibration signal to the self-calibration unit. The self-calibration unit determines an error signal based on the first calibration signal and the second calibration signal. The self-calibration unit obtains a calibrated third sampling signal based on the second sampling signal and the error signal.