This invention is related to the method providing computation of the signal frequency components in an acceptable accuracy in contravention of the shifts in the phase and the magnitude information caused by asynchronous sampling of the signals in the process of asynchronous sampling of metal detectors wherein the received signal by the receiver unit (4) divided into time intervals, say timing values those are far shorter than the sampling period and correspond to nearest probable sampling of the ADC (6); providing the computation of the sine and cosine coefficients or exponents of time constant coefficients of the said timing value from previously located or dynamically generated coefficient table; resulting the elimination of the requirement of synchronous sampling and the requirement of the signal period is multiple of the sampling period.

Disclosed is a method that includes generating a prediction consistency value that indicates a consistency of prediction of an object in an input image with respect to class prediction values for the object in an input image from classification models to which the input image is input, and identifying a class of the object. Identifying the class of the object includes, in response to a class type being determined, based on the prediction consistency value, of the object being determined to correspond to a majority class, identifying a class of the object based on a corresponding class prediction value output for the object from a majority class prediction model, and in response to the class type of the object being determined to correspond to a minority class, identifying the class of the object based on another corresponding class prediction value output for the object from a minority class prediction model.

The present disclosure provides a successive approximation method of three-state quantization and a successive approximation analog-to-digital converter circuit. The method includes for a first successive approximation of the arbitrary analog input signal between 0 and 1, comparing it with a quantization line 1/2; performing a second successive approximation according to a state of the first successive approximation; and by analogy up to a N.sup.th successive approximation, in case that a certain successive approximation is the state three during the comparison process, ending the approximation, indicating that the interval where the signal is located has been found.

Continuous time pipeline, level-crossing (LC), analog-to-digital converters (ADCs) use a plurality of stages from a first stage to a last stage. Each stage has an array of comparators that are provided with an array of reference voltage levels. Each stage is configured to detect level crossings of increasing fineness compared to the preceding stage such that the accuracy of a digitized representation of an input signal can be increased by adding stages as well as increasing the number of comparators in each stage. The voltage error in the digitized representation of the signal that remains after each stage provides the input to the subsequent stage. The continuous time pipeline LC ADCs are also applied to analog signal processing and software defined radios.

A motor driver includes an analog-to-digital converter (ADC) which, when a voltage sensing signal detected at a phase voltage of a specific coil in a floating period is input, samples the input voltage sensing signal at each of a plurality of sampling points and converts the voltage sensing signal into digital voltage sampling data and a back electromotive force voltage determination unit which determines a back electromotive force voltage of the specific coil on the basis of a plurality of pieces of the digital voltage sampling data.

A method for motor voltage reconstruction by Analog to Digital Converter (ADC) oversampling and averaging includes measuring a first phase voltage with an ADC, the first phase voltage proportional to a first duty cycle of a first Pulse Width Modulation (PWM) signal. A second phase voltage is measured with the ADC, the second phase voltage proportional to a second duty cycle of a second PWM signal, wherein the first PWM signal and the second PWM signal control consecutive phases of a three-phase motor. A third duty cycle of a third PWM signal of the three-phase motor is reconstructing from the first phase voltage and the second phase voltage.

The present disclosure provides a measurement application device comprising a measurement interface configured to receive an analog measurement signal, an analog-to-digital converter coupled to the measurement interface, wherein the analog-to-digital converter is configured to convert the analog measurement signal into a digital data stream, a segmented memory coupled to the analog-to-digital converter, wherein the segmented memory comprises a plurality of memory segments and is configured to store digital data stream sections of the digital data stream into each one of the memory segments, and a trigger unit coupled to the segmented memory, wherein the trigger unit is configured to create a trigger output signal based on a trigger condition definition and the digital data stream stored in each one of the single memory segments. Further, the present disclosure provides a respective method.

A digital signal processing circuit includes an analog gain compensator that compensates for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal; an analog-to-digital converter (ADC) that converts the compensated baseband signal into a first digital signal; a plurality of filtering circuits that generate a second digital signal from the first digital signal; and a control circuit. Each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and a performs down-sampling. The control circuit generates an analog gain control signal for controlling the analog gain based on the second digital signals and a digital gain control signal for controlling the digital gain.

An integrated circuit includes an analog-to-digital converter (ADC), associated with a thermal sensor, to determine a present power supply value of a power supply voltage for the thermal sensor. E-fuse registers store a set of calibrated temperature values, from the thermal sensor, for each power supply value of a plurality of power supply values. Control logic is coupled to the ADC and the e-fuse registers. The control logic reads the present power supply value from the ADC and generates, based on the present power supply value and the plurality of power supply values, a calibration equation that relates calibrated temperature values to thermal sensor values for the present power supply value.

Some embodiments relates to the technique, including systems and methods, for use in analog-to-digital conversion (ADC). A sampling system is presented for sampling an input analog signal including a train of pulses of a predetermined shape and allowing a recovery of the degrees of freedom of the signal. The sampling system includes: a kernel for selectively passing components of an input signal, and an integrate and fire time encoding machine (IF-TEM), wherein the kernel has a size of kernel support set being in a predetermined relation with a number of degrees of freedom in the finite rate of innovation signal.