Disclosed are an encoder signal sampling method and device. According to the method and device, a data frequency of the encoder is obtained, a clock frequency is determined according to the data frequency, a high-frequency clock signal is generated based on the clock frequency, an input signal of the encoder is sampled based on the high-frequency clock signal to obtain a sampled signal, and finally denoising processing is performed on the sampled signal based on a preset algorithm by a processer.

A low voltage drive circuit (LVDC) includes a data splitter operable to split transmit digital data into a plurality of streams of digital data. The LVDC further includes a plurality of signal generators operable to receive the plurality of streams of digital data at a plurality of data rates and generate a plurality of analog outbound data signals for the plurality of streams of digital data. A first signal generator receives a first stream of digital data of the plurality of streams of digital data at a first data rate. A second signal generator receives a second stream of digital data of the plurality of streams of digital data at a second data rate. The LVDC further includes a signal combiner operable to combine the plurality of analog outbound data signals into analog outbound data and a drive sense circuit operable to drive the analog outbound data onto a bus.

An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).

A digital signal processor (DSP) for a receiver and a method for processing signals in a receiver are provided. The DSP comprises a processor configured to: receive a digital signal at a symbol rate in a frequency domain; and compensate an impairment of the digital signal in the frequency domain.

A radio receiver device comprises an analogue-to-digital converter clocked by a first clock signal which receives a radio signal. A digital circuit portion receives a digital signal produced by the analogue-to-digital converter and comprises digital processing units clocked by a second clock derived from the first clock and which produce an output signal at an output sample rate. A counter clocked by the second clock counts samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag synchronised to the first clock. The counter is enabled when the flag is set and sets a trigger flag when the count exceeds a predetermined threshold. A buffer receives the output signal and is enabled when the trigger flag is set.

An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

For cross-channel spectral analysis of measurement data from multiple recording units with independent sampling clocks, a processing method corrects phase mismatch between the data received over the different channels. Blocks of sampled measurement data are buffered in a hardware logic circuit and timestamps are associated with successive blocks through a hardware interrupt to a GPS receiver of each recording unit. For each first channel data block, the block's starting point, a closest point in time in a data block of the second channel, and the starting point of that second channel data block are determined, using GPS timestamps associated with those data blocks, nominal sampling rate and block size. Phase correction based on the time offset between starting points of the pairs of data blocks and the interval between starting points of successive blocks is applied in the frequency domain after a time-to-frequency domain transformation. Multiple frames of phase-corrected spectra may then be averaged. Only a subset of samples in each data block need be used based upon a specified overlap ratio.

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.