A chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit is provided. The chip state monitoring circuit is built in a chip, and can sense a state signal of the chip and transmit the state signal to a chip configuration circuit after performing amplification and analog-to-digital conversion, such that the chip configuration circuit can monitor a state and provide a timely feedback or response, thereby improving reliability and a service life of the chip. The chip state monitoring circuit uses a brand new self-balancing differential signal integration and amplification circuit. With a built-in positive coefficient integration network and negative coefficient balancing network, the self-balancing differential signal integration and amplification circuit can perform amplification by required times to enter a self-balancing stable state, thereby achieving fixed-multiple amplification without timed reading. The control method is simple and flexible.

An analog-to-digital converter has a first digital signal generator that generates a first digital signal based on whether or not a sampling signal of an input signal is equal to or lower than a signal corresponding to a second reference signal higher than a first reference signal, a first slope generator to generate a first slope signal that changes with time from the sampled and held signal equal to or lower than the first reference signal, a second slope generator to generate a second slope signal that changes with time from the sampled and held signal to a signal level equal to or lower than the second reference signal, and a second digital signal generator that generates a second digital signal based on a time at which the first slope signal matches the first reference signal or a time at which the second slope signal matches the second reference signal.

A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

An ADC sampling data identification method and system, integrated circuit and decoding device are disclosed. The ADC sampling data identification method includes in the integrated circuit, converting sampling data from n time interleaved ADC chips into serial data, generating a preamble sequence, combining the serial data with the generated preamble sequence to obtain new serial data, sending the new serial data to a decoding device, generating a clock signal that matches the new serial data, and sending the clock signal to the decoding device; and in the decoding device, receiving the new serial data and the clock signal from the ADC integrated circuit, obtaining the preamble sequence for combining according to an agreement with the ADC integrated circuit, and identifying a start position of the sampling data from the time interleaved ADC chips.

A synchronization detection device includes: a correction unit configured to correct sampled data of a waveform on which a dither signal is superimposed, for each period of a reference signal in accordance with a period of the dither signal; a multiplication unit configured to multiply the corrected sampled data by a weight coefficient that is different for each level of the reference signal and associated with a timing of the reference signal; and an averaging unit configured to derive, as a detection result, an average of a result of the multiplication of the corrected sampled data by the weight coefficient.

Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

Blood pressure detection signal sampling and compensation methods and apparatuses, and an example blood pressure signal collection system are described. One example method described includes controlling an electrocardiogram (ECG) sampling module and a photoplethysmogram (PPG) sampling module to simultaneously sample a standard periodic signal. Sampling frequencies and sampling end times are separately obtained. A sampling start time and a sampling frequency of the ECG sampling module or the PPG module is then compensated so that a sampling frequency deviation is less than a preset frequency threshold and a sampling end time difference is less than a preset time threshold.

A distributed data acquisition system comprising multiple, physically unconnected, data acquisition units that can be in wireless communication with a remote host, timestamps measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. Each unit has a GPS receiver for deriving an absolute time. An analog-to-digital converter samples measurement data using a sampling clock. A hardware logic circuit, such as a field programmable gate array, associates batches of the measurement data with corresponding timestamps representing the current absolute time. A time offset bias may be compensated by a comparison of timestamps with nominal time based on start time and nominal sampling rate. Additionally, the sampling clock may be synchronized using time pulses from the GPS receiver. An initial start of ADC sampling by all data acquisition units may be also synchronized.