A method uses a distributed data acquisition system with multiple, physically unconnected, data acquisition units, that can be in wireless communication with a remote host, to timestamp measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. A current absolute time is derived from messages received from a satellite radio beacon positioning system (GPS). Measurement data is sampled by each unit at a specified sampling rate. Using hardware logic, batches of sampled data are associated with corresponding timestamps representing the absolute time at which the data was sampled. Data and timestamps may be transmitted to the host. A time offset bias is compensated by comparing timestamps against a nominal time based on start time and nominal sampling rate. The sampling clock rate may be disciplined using time pulses from the GPS receiver. An initial start of data sampling by all units can also be synchronized.

Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

Disclosed are an encoder signal sampling method and device, which relate to the technical field of servo control. According to the method and device, a data frequency of the encoder is obtained, a clock frequency is determined according to the data frequency, a high-frequency clock signal is generated based on the clock frequency, an input signal of the encoder is sampled based on the high-frequency clock signal to obtain a sampled signal, and finally denoising processing is performed on the sampled signal based on a preset algorithm by a processer. The input signal of the encoder is sampled by utilizing the high-frequency clock signal to obtain more sampling points so that enough signal samples are obtained for subsequent data analysis and denoising. The influence of the noise signal on the sampled signal is smaller since a proportion of the valid signal in the signal sample is obviously larger than a proportion of the noise signal with the high-frequency clock signal, so that the accuracy of the sampled signal is ensured.

Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

Diverse applications in particle physics experiments and emerging technologies such as Lidar are driving performance increase and cost reduction in giga-hertz sampling-rate high-resolution data conversion. In applications such as these, critical aspects of the data may occur only during relatively short nanosecond portions of observation periods lasting microseconds. Data acquisition architectures that key in on regions of the data containing activity, digitize the data, and provide info to accurately measure the position of the data in time relative to a time reference are described. These architectures may facilitate system implementation and reduce overall system cost.

A radio receiver device, arranged to receive a radio signal modulated with a plurality of data symbols, comprises an analogue-to-digital converter that is clocked by a first clock signal and is arranged to receive the radio signal and produce a digital signal. A digital circuit portion, arranged to receive the digital signal produced by the analogue-to-digital converter, comprises digital processing units that are clocked by a second clock derived from the first clock and arranged to process the digital signal and produce an output signal at an output sample rate. A counter, clocked by the second clock, counts a number of samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag which is synchronised to the first clock. The counter is enabled only when the synchronised flag is set. The counter is arranged to set a trigger flag when the number of samples exceeds a predetermined threshold. A buffer is arranged to receive the output signal and is enabled only when the trigger flag is set.

Provided is a light detecting apparatus including: a phase locked loop portion that generates a sampling clock based on a synchronization signal output from a light source that emits pulsed laser light; an A/D convertor that performs sampling of signal light output from a sample as a result of radiating the laser light thereon in accordance with the sampling clock; and a received-data processing portion that accommodates, every time N items of the sampling data are continuously acquired, the N items of data in a single data sequence. The phase locked loop portion is provided with a clock generating portion that generates a clock that has a frequency that is N times a pulse frequency of the laser light and that is synchronized with a phase of the laser light, and a delay adjusting portion that generates the sampling clock by adjusting a delay amount of the generated clock.