A light detection and ranging (lidar) receiver may include a first frequency filter to pass a first range of frequencies of an analog signal. The lidar receiver may include a second frequency filter to pass a second range of frequencies of the analog signal that is different from the first range of frequencies of the analog signal. The lidar receiver may include a first analog-to-digital converter (ADC) to derive a first digital signal based on the first range of frequencies of the analog signal using a first sampling rate. The lidar receiver may include a second ADC to derive a second digital signal based on the second range of frequencies of the analog signal using a second sampling rate that is different from the first sampling rate.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levelsa functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

The disclosed apparatus, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a structure operative to receive a plurality of analog signals, a signal encoder configured to encode the plurality of received analog signals into a single encoded analog composite signal based on a coding scheme operating under a first code rate, a signal reconstruction module configured to segregate and reconstruct the single encoded digital composite signal into a re-encoded digital composite signal in accordance with the coding scheme operating under a second code rate. In addition, a signal decoder configured to decode the digital composite signals based on the coding scheme operating under the second code rate, and to output digital signals, in which each digital signal in the plurality of digital signals corresponds to a respective analog signal of the plurality of received analog signals.

A technology capable of sampling sensor signals in a plurality of channels simultaneously is realized. An input unit is capable of inputting sensor signals from a plurality of sensors, and includes an analog-to-digital (AD) conversion unit which is disposed with respect to each of the plurality of sensors and acquires the sensor signal from each of the sensors and converts the sensor signal into a digital signal, and a timing control unit which controls timing at which a plurality of the AD conversion units acquire the sensor signal for each of the AD conversion units according to a sampling period of each of the plurality of sensors.

An apparatus includes a plurality of pixels, a plurality of circuits arranged correspondingly to the plurality of pixels, and an output line connected to the plurality of circuits. Each of the circuits generates a signal by converting an analog signal at a first conversion rate and a signal by converting, at a second conversion rate, the analog signal used for generating the signal converted at the first conversion rate. The circuit has a signal obtaining unit configured to obtain a difference signal corresponding to a difference between a signal converted at the first conversion rate and a signal converted at the second conversion rate.

A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levelsa functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

An object of the present invention is to efficiently compress a plurality of kinds of data series with different sampling rates. A data compression device has a grouping unit and a compression unit. The grouping unit groups a plurality of kinds of data series with different sampling rates. The compression unit compresses the data series grouped by the grouping unit.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.