A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.

In one embodiment, a method for monitoring a heartbeat includes receiving a heartbeat signal, the heartbeat signal including heartbeat cycles. The method also includes determining a region of interest (ROI) of the heartbeat cycles based on an identifying feature of each heartbeat cycle of the heartbeat cycles. The ROI includes a first portion of a period of a first heartbeat cycle. The method also includes sampling the first portion of the heartbeat cycle within the ROI at a first sampling rate and sampling a second portion of the heartbeat cycle outside of the ROI at a second sampling rate less than the first sample rate.

A method for operating an analog-to-digital converter to convert a signal includes calculating a signal parameter in a spectral sub-range of the signal to be converted. The spectral sub-range includes a frequency range of a potential sampling frequency range of the analog-to-digital converter, which does not include frequencies of at least one other sub-range of the sampling frequency range. The method further includes determining a sampling frequency of the analog-to-digital converter by using the signal parameter and operating the analog-to-digital converter using the determined sampling frequency.

An apparatus includes a plurality of pixels, a plurality of circuits arranged correspondingly to the plurality of pixels, and an output line connected to the plurality of circuits. Each of the circuits generates a signal by converting an analog signal at a first conversion rate and a signal by converting, at a second conversion rate, the analog signal used for generating the signal converted at the first conversion rate. The circuit has a signal obtaining unit configured to obtain a difference signal corresponding to a difference between a signal converted at the first conversion rate and a signal converted at the second conversion rate.

A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.

A method and circuit for recovering data from a digital bitstream received from an analog to digital converter includes asynchronously oversampling the digital bitstream at a sampling rate dictated by an estimate of a clock rate of the analog to digital converter and a nominal oversampling factor. The method and circuit also includes calculating widths of bits of the digital bitstream, and calculating a learned oversampling factor using the calculated widths of a predetermined number of bits of the digital bitstream and a minimization function. The method and circuit also includes calculating data bits to be inserted to a digital filter for digestion using the calculated widths of the bits of the digital bitstream and the learned oversampling factor.

The present disclosure provides an analog-to-digital converter system comprising a sampler configured to sample an input signal and provide at least two output signals with a predetermined output sample rate, and an analog-to-digital converter for each one of the output signals and configured to convert the respective output signal into a digital signal with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate. Further, the present disclosure provides a respective method.

An array-based Compressed sensing Receiver Architecture (ACRA) includes an antenna array with two or more antennas connected to two or more ADCs that are clocked at two or more different sampling rates below the Nyquist rate of the incident signals. Comparison of the individual aliased outputs of the ADCs allows for estimation of signal component characteristics, including signal bandwidth, center frequency, and direction-of-arrival (DoA). Multiple digital signal processing (DSP) techniques, such as sparse fast Fourier transform (sFFT), can be employed depending on the type of detection or estimation.