A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including a first sample and hold circuit for sampling an input signal, a first ADC configured to generate a digital representation of the sampled input signal from the first sample and hold circuit, and a first digital-to-analog converter (DAC) responsive to the output of the first ADC and configured to generate an analog representation of the digital representation of the sampled input signal. A control processor is provided and configured to generate a digital control signal. A current control circuit is responsive to the digital control signal for generating an analog current control signal for selectively altering a characteristic of at least one of the first ADC and the first DAC.

An image sensing device includes a readout circuit suitable for sequentially generating a plurality of image signals corresponding to each pixel signal, based on a ramp clock and a count clock; and a clock generation circuit suitable for generating the ramp clock and the count clock having different frequency relationships depending upon generation periods of the image signals, based on a gain code signal corresponding to an analog gain.

Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically, to transitioning between clock frequencies to convert analog signals to digital signals at dynamic sampling rates. In an example embodiment, a device including an analog-to-digital converter (ADC) and a control circuit coupled to the ADC is provided. The ADC is configured to receive a first analog signal, receive a first clock signal, and generate a first set of digital values corresponding to the first analog signal based on the first clock signal. The control circuit is configured to determine that a change in the first set of digital values satisfies a first threshold value and increase the first clock signal from a first frequency to a second frequency in response to determining that the change in the first set of digital values satisfies the first threshold value.

A motor controller with a data bit expansion mechanism is provided. The motor controller sets a plurality of pieces of target waveform characteristic data that are used respectively within a plurality of magnetic pole position time intervals to output a motor control output instruction. The motor controller, according to each of the plurality of pieces of target waveform characteristic data, generates a plurality of pieces of sub-target waveform characteristic data in a bit number expansion instruction. The plurality of pieces of sub-target waveform characteristic data are used respectively within a plurality of bit expansion time intervals. The bit number of each of the plurality of pieces of sub-target waveform characteristic data is smaller than an upper limit bit number. The motor controller generates a plurality of bit-expansion waveforms according to the bit number expansion instruction for controlling a motor.

In general, according to one embodiment, a semiconductor integrated circuit includes the following configuration. A first converter samples a first digital value from an analog signal based on a first clock signal. A second converter samples a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase. A first processing circuit calculates phase shifts of the first and second clock signals based on the first and second digital values and using a first frequency of a third clock signal. A second processing circuit generates a control signal for correcting the phase shifts of the first and second clock signals based on the phase shifts calculated by the first processing circuit and using a second frequency of a fourth clock signal. The second frequency is 2.sup.m times the first frequency.

A digitizing circuit includes a port connectable to a device under test (DUT), an integrating analog-to-digital converter (ADC), a high-speed ADC, one or more processors to apply a digital filter to output samples of the high-speed ADC to produce filtered samples, find differences between the filtered samples and samples from the integrating ADC to produce error values, and add the error values to the output samples of the high-speed ADC. A method of producing a digital signal includes receiving an input analog signal at an integrating analog-to-digital converter (ADC) and a high-speed ADC, applying a digital filter to output samples of the high-speed ADC to produce filtered samples, the digital filter matched to timing and filtering of the integrating ADC, finding differences between the filtered samples to output samples of the integrating ADC to produce error values, and adding the error values to the output samples of the high-speed ADC.

A method is provided for performing compressed sensing of a spectrally-sparse signal within a given spectral band. The received signal being mixed over a sensing frame with a pulse train scrolling with a repetition frequency linearly modulated over time within this frame. The result of mixing is filtered by low-pass filtering and sampled at a non-uniform rate equal to the repetition frequency, to result in complex samples representative of the received signal. The spectrum of the received signal can be estimated by weighting, using the complex samples, the spectral values of a pulse into a plurality of frequency equidistributed in the band, and by summing up these weighted values for each of these frequencies. An estimate of the received signal is thereby deduced by inverse Fourier transform. The spectral band can be scanned based on the spectrum thus estimated.

A bit error rate testing method includes: sampling, by an analog-to-digital converter circuit, a symmetric signal to generate output digital codes; identifying a starting digital code in the output digital codes; storing the starting digital code and first digital codes, which follow the starting digital code in the output digital codes, into a first register circuit in an order as second digital codes, in which the starting digital code and the first digital codes correspond to one cycle of the symmetric signal; storing the starting digital code and the first digital codes into a second register circuit in a reversed order; shifting the starting digital code and the first digital codes in the second register circuit to generate third digital codes; and determining a bit error rate of the analog-to-digital converter circuit according to a difference between a corresponding second digital code and a corresponding one third digital code.

A multi-Nyquist correlator. An example system includes a first analog to digital converter (ADC) configured to operate at a first sampling frequency and a second ADC configured to operate at a second sampling frequency different from the first sampling frequency. Each of first and second ADCs may receive a plurality of radio frequency (RF) pulses, and respectively generate first and second ADC outputs. First and second digital receivers of the system respectively process the first and second ADC outputs and respectively generate first and second pluralities of pulse description data signals (PDDs). A correlator of the system corelates PDDs of the first and second pluralities of PDDs, to determine which RF pulses received are related to each other. With this relationship determined, the true Nyquist zone can be determined, and the true RF frequency can be calculated. A frequency measurement module may be used to measure frequency of received signal.