Amplifiers, preamplifiers, and other circuits may have registers that are assigned to store data corresponding to certain functions. When the data stored in the registers are no longer needed, the registers may be assigned to store data corresponding to other functions, such as signal acquisition. The registers can be logically grouped into a virtual memory bank. The memory bank may store new data to a first register, and move data from the first register to a second register when new data arrives. In some embodiments, these registers and memory control circuit can be implemented within a preamplifier circuit.

In order to provide a highly precise analog/digital conversion system in which an output error of an AD converter is small, sampling is performed at a certain sampling period S from the start time of a measurement period TL to the (N?1)-th sampling when the measurement period TL does not correspond to the sampling period S multiplied by the number of samplings N, the N-th sampling is performed at a timing when a time interval between the (N?1)-th sampling and the N-th sampling is equal to the sampling period S multiplied by a predetermined coefficient k, and the k value is set to a non-integer optimum value evaluated in advance in accordance with the N value in order to minimize an error of the detection value of the AD converter.

A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.

A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.

A photonic compressive sampling system includes a photonic link with at least one electro-optic modulator that modulates a continuous wave optical energy with both an electrical analog signal and a pseudorandom bit sequence signal. A photodetector receives the modulated optical energy from the electro-optic modulator, and an electrical digitizer digitizes the output from the photodetector. The system enables signal recovery beyond the Nyquist limit of the digitizer. The signal being recovered has a sparse (low-dimensional) representation and the digitized samples are incoherent with this representation. An all-photonic system can faithfully recover a 1 GHz harmonic signal even when digitizing at 500 MS/s, well below the Nyquist rate.

A method of analog to digital conversion for a field device having an analog to digital converter system (ADCS) including an ADC and a plurality of filters. An analog sensing signal is received from a sensor which measures a level of a physical parameter in a manufacturing system that runs a physical process. A level of the physical parameter is compared to reference noise data. Based on the comparing, at least one ADCS parameter is determined. The ADCS parameter is implemented to configure the ADCS. The ADCS is utilized with the ADCS parameter to generate a filtered digitized sensing signal from the analog sensing signal.

A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.

Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method also includes mapping the sampled received signal onto a frequency grid of sinusoids, where each sinusoid has a signal amplitude and a signal phase. The method further includes estimating the signal amplitude and the signal phase for each sinusoid in the frequency grid. In addition, the method includes computing an average background power level and detecting signals with power higher than the average background power level. The non-uniform sampling interval varies predictably.

An AD conversion device includes an AD converter that outputs an analog signal as sampling data for every sampling point based on a sampling frequency, a controller, and a storage circuit, the controller includes a buffer memory which temporarily stores the sampling data from the AD converter in time series and from which the sampling data is read out in time series, and a decimation controller, the decimation controller outputs a write-enable signal indicating write-enabled for the selected sampling data in the decimation region and the sampling data in the high-speed sampling region, and outputs decimation bit information indicating whether the sampling data is the sampling data of the decimation region or the sampling data of the high-speed sampling region, and the storage circuit stores the sampling data stored in the buffer memory in association with the decimation bit information, in response to the write-enable signal.