A CMOS image sensor comprises an array of pixels. A column of the pixel array is coupled to a readout column. The readout column is couple to a readout circuitry (RC) that reads out image data from the pixel array. The RC comprises a sampling switch which is coupled to a 1-column successive approximation register (SAR) analog-to-digital converter (ADC). The 1-column SAR ADC comprises a differential comparator, a local SAR control, and a digital-to-analog converter (DAC). The sampling switch is coupled between a readout column and a non-inverting input of the differential comparator. An image readout method reads one pixel with two conversions through the RC. The RC is operated by the local SAR control to set the DAC based on comparator output, and upon which a reset digital value is obtained and stored. An overall reduced algorithm calculation is achieved herein.

The present disclosure relates to an imaging element, a driving method, and electronic equipment that enable imaging to be performed at higher speed. The imaging element includes a pixel array in which a plurality of pixels are arranged in a matrix shape, an AD converter that performs AD conversion in parallel on pixel signals that have been output from the plurality of pixels for each column of the plurality of pixels arranged in the pixel array, and a reference signal generator that generates a reference signal that the AD converter refers to when the AD converter performs AD conversion on a pixel signal for an identical pixel signal, the reference signal having a waveform that includes a slope having a constant gradient. Then, when the AD converter performs, on the identical pixel signal, multi-sampling for performing sampling during a P-phase period and sampling during a D-phase period at least once or more, the reference signal generator generates a reference signal in which, from among a plurality of slopes during the D-phase period, a sampling period of a second slope has been set to be shorter than a sampling period of a first slope. The present technology is applicable, for example, to a CMOS image sensor including a column-parallel ADC.

In a digital signal processing circuit that performs AD conversion using a comparison device and a counter, the speed of the AD conversion is increased. An attenuation unit, in a case where the level of an input signal exceeds a predetermined threshold value, attenuates the input signal and outputs it as an output signal. The comparison device compares the output signal with a predetermined reference signal that changes with lapse of time, and outputs the comparison result. The counter counts a count value until the comparison result is inverted and outputs a digital signal indicating the count value. The digital signal processing unit performs multiplication processing on the digital signal.

A digital closed loop control system. An output signal is detected with the aid of an analog-to-digital converter. A correction value is subtracted from the output signal prior to the analog-to-digital conversion and this correction value is added up again after the analog-to-digital conversion. The correction value in this case may be dynamically adapted. In this way, the analog-to-digital converter may be operated in a narrow conversion range.

An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).

There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.

Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

A circuit includes a first amplifier that first compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, second compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal in the first and second operation periods based on first and second comparison results; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, stops an operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which the first operation period starts, and generates a second output signal based on the first output signal in the first operation period and the second operation period.

There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.

It is an object of the present technology to provide an image sensor capable of reducing crosstalk in an AD conversion unit. The image sensor includes: capacitors in an even-numbered column region; and a capacitor in an odd-numbered column region disposed facing the capacitors in the even-numbered column region with different areas.