An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (V.sub.th) to a pixel signal (S.sub.VSL). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.

An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.

A measurement circuit device for a vehicle includes a power transistor and a voltage measurement circuit coupled to the power transistor that measures a voltage across the power transistor. The measurement circuit device also includes a microcontroller that determines a junction temperature using the measured voltage and adjusts a capacity of the power transistor based on the determined junction temperature. In some embodiments, the measurement circuit device may include a clamping device that clamps the voltage across the transistor when the transistor is off. The measurement circuit device may also include an analog-to-digital converter that converts the measured voltage from an analog value to a digital value.

In some examples, a sensor apparatus comprises: a pixel cell configured to generate a voltages, the pixel cell including a photodiode configured to generate charge in response to incoming light, and a charge storage device to convert the charge to a voltage; an integrated circuit configured to: determine a first captured voltage converted by the charge storage device during a first time period; compare the first captured voltage to a threshold voltage value; and in response to determining that the first captured voltage meets or exceeds the threshold voltage value: determine first time data corresponding to the first time period; and prevent the charge storage device from further generating a charge; and an analog-to-digital converter (ADC) configured to generate a digital pixel value based on the first captured voltage, and a memory to store the digital pixel value and the first time data.

A solid-state imaging device includes: a pixel unit that outputs a pixel signal corresponding to an amount of incident light; an A/D converter that performs A/D conversion on the pixel signal; and a D/A conversion circuit that generates a reference signal to be used by the A/D converter. The D/A conversion circuit includes a first buffer circuit that outputs a base voltage VTOP for generating the reference signal, and the first buffer circuit includes a differential pair circuit including a first transistor and a second transistor, and a suppression circuit that suppresses a variation in the base voltage by canceling out a characteristic difference between the first transistor and the second transistor.

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold.

A method of operating an image sensor includes generating an analog pixel signal, including a reset component and an image component, based on incident light received by a pixel in the image sensor. Operations are performed to repeatedly sample the reset component of the analog pixel signal using a ramp signal, during a first time interval, and then repeatedly sample the image component of the analog pixel signal using the ramp signal, during a second time interval subsequent to the first time interval. A digital signal corresponding to an effective image component of the incident light is then generated. This digital signal is based on the repeatedly sampled reset component of the analog pixel signal and the repeatedly sampled image component of the analog pixel signal. In addition, during both the first and second time intervals, the ramp signal decreases in magnitude and increases in magnitude.

The present disclosure relates to an imaging element, a driving method, and electronic equipment that enable imaging to be performed at higher speed. The imaging element includes a pixel array in which a plurality of pixels are arranged in a matrix shape, an AD converter that performs AD conversion in parallel on pixel signals that have been output from the plurality of pixels for each column of the plurality of pixels arranged in the pixel array, and a reference signal generator that generates a reference signal that the AD converter refers to when the AD converter performs AD conversion on a pixel signal for an identical pixel signal, the reference signal having a waveform that includes a slope having a constant gradient. Then, when the AD converter performs, on the identical pixel signal, multi-sampling for performing sampling during a P-phase period and sampling during a D-phase period at least once or more, the reference signal generator generates a reference signal in which, from among a plurality of slopes during the D-phase period, a sampling period of a second slope has been set to be shorter than a sampling period of a first slope. The present technology is applicable, for example, to a CMOS image sensor including a column-parallel ADC.

A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.