The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

A pipelined ADC that does not wait for the residue of a signal to settle to be delivered to the next stage of the pipeline, and thus passes signals to subsequent stages at faster than conventional speeds. A pipelined ADC is used that processes signals representing the boundaries of the search space. Thus, each stage does not necessarily receive the signal as pre-processed by the prior stage, but rather the search space boundaries as pre-processed by the prior stage. Reducing the “search space” of the ADC is equivalent to creating the residues in each step of a pipeline as in the prior art. An ADC operating in this fashion operates without error even if the residual search space boundary outputs from one state are presented to the next stage before the outputs have settled, and can run faster for a given power and bandwidth.

Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.

Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.

One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog converter, a first analog-to-digital converter, and a second analog-to-digital converter. The capacitive digital-to-analog converter includes a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device while the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage. The second analog-to-digital converter is coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device.

An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

In accordance with an embodiment, a method for operating an analog-to-digital converter (ADC) includes: determining a trip point of a comparator of the ADC by applying a first signal having a first slope to an input of the ADC, and monitoring an output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined trip point of the comparator, monitoring values of an output code of the ADC in response to the second signal, and generating statistical information based on the monitored values of the output code, where the second signal is a static signal or has as second slope less than the first slope.

The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.