Disclosed are an analog-to-digital conversion circuit, an analog-to-digital conversion device, and a digital x-ray imaging system. The analog-to-digital conversion circuit includes a first reference voltage source, a second reference voltage source, a first analog-to-digital converter connected to the first reference voltage source, a second analog-to-digital converter connected to the second reference voltage source, a connecting circuit connected to the first analog-to-digital converter and the second analog-to-digital converter, respectively, and a current source having negative temperature coefficient configured to be connected to the first reference voltage source and the second reference voltage source, respectively.

An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the i.sup.th pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.

An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into first digital codes. A first converter circuitry in the converter circuitries performs a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate first and second valid signals, and determines whether to set the second digital code to be a first predetermined digital code or a second predetermined digital code according to the first and the second valid signals. The second valid signal is a delay signal of the first valid signal.

An analog-to-digital converter includes a voltage-to-delay device, such as a pre-amplifier array, for generating a delay signal based on a first voltage, and delay-based stages for generating digital signals based on the delay signal. In operation, the delay signal is transmitted to a first delay-based stage, or to an intermediate delay-based stage, bypassing the first delay-based stage, to overcome non-linearity of previous stages. If desired, different pre-amplifiers may be used to generate signals for calibration of different delay-based stages. The present disclosure may also involve converting to pseudo-static signals before signals are handed over to a calibration engine, to ease timing and preserve interface area and power. If desired, simple delay elements may be used to correct for non-linearity in a delay-based analog-to-digital converter. The present disclosure may be employed, if desired, in connection with any suitable cascade of non-linear stages.