Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.

An image sensor including a pixel of a first tap. a pixel of a second tap. an operational amplifier configured to perform an auto zeroing operation with a pixel signal of the pixel of the second tap applied, and perform an operation for comparison between a ramp voltage and a signal output from the pixel of the first tap, with a pixel signal of the pixel of the first tap applied, and a counter circuit configured to generate a digital code in response to an output of the operational amplifier.

A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.

Provided is a photoelectric conversion device including: a pixel configured to generate a first signal in accordance with an incident light by photoelectric conversion; an amplifier unit configured to amplify the first signal to output a second signal; and a comparator unit configured to compare a voltage of the second signal with a voltage of a reference signal. A slope of the ramp waveform included in the reference signal can be switched between a first slope α and a second slope β, the reference voltage used for determining a setting of a gain in the amplifier unit or the comparator unit can be switched between a first reference voltage Vref1 corresponding to the first slope α and a second reference voltage Vref2 corresponding to the second slope β, and α/β≠Vref1/Vref2 is satisfied.

An image pickup device, comprises: a pixel configured to output a signal based on a light reception amount; and an AD conversion unit. The AD conversion unit includes: an amplifier circuit configured to amplify a signal that is output from the pixel; a comparator circuit including an output node for outputting a comparison result signal generated by using an output signal from the amplifier circuit and a ramp signal; a memory configured to hold a digital value corresponding to the output signal, based on a result of the comparator circuit; a gain switching circuit configured to switch a gain of the amplifier circuit; and a ramp signal switching circuit configured to switch a slope of the ramp signal. The gain switching circuit and the ramp signal switching circuit are electrically connected to the output node.

A digital-to-analog converter comprising: a plurality of capacitances and a plurality of switches. A capacitance among the plurality of capacitances, of which the number corresponds to the resolution of the analog signal to be output, is used as a voltage value generation capacitance, so as to generate a voltage value based on the reference voltage to be added or subtracted, by switching a node to which the second terminal is connected by a corresponding switch. A remaining capacitance, which is not used as the voltage value generation capacitance among the plurality of capacitances, is used as a gain adjustment capacitance, so as to adjust gain of a voltage value based on the reference voltage to be added or subtracted, by holding a node to which the second terminal is connected by a corresponding switch.

A digital to analog converter (DAC) can include a current mode DAC to receive an OC word from digital logic indicating an amount of current to add to or remove from sources of respective transistors of an amplifier and generate a current based on the OC word, an active output stage including a positive current mirror and a negative current mirror to generate a positive current and a negative current based on at least a portion of the generated current, and a plurality of outputs including a plurality of sink outputs and a plurality of source outputs to provide the positive and negative currents to the sources of the respective transistors.