A successive-approximation type A/D conversion circuit includes: a selection signal input terminal that receives a selection signal; a clock input terminal that receives a clock signal; a main circuit that generates digital data in synchronization with the clock signal during an active period; a data output terminal; a data output circuit that outputs the digital data as a serial signal from the data output terminal during the active period; and a level adjustment circuit. The data output circuit outputs the serial signal by setting a signal level of the data output terminal to a first level and setting the signal level to the first level or a second level during the active period. When the signal level has the second level at the time of switching from the active period to a non-active period, the level adjustment circuit changes the signal level from the second level to the first level.

An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.

An image pickup device, comprises: a pixel configured to output a signal based on a light reception amount; and an AD conversion unit. The AD conversion unit includes: an amplifier circuit configured to amplify a signal that is output from the pixel; a comparator circuit including an output node for outputting a comparison result signal generated by using an output signal from the amplifier circuit and a ramp signal; a memory configured to hold a digital value corresponding to the output signal, based on a result of the comparator circuit; a gain switching circuit configured to switch a gain of the amplifier circuit; and a ramp signal switching circuit configured to switch a slope of the ramp signal. The gain switching circuit and the ramp signal switching circuit are electrically connected to the output node.

A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer 2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.

Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

An example apparatus includes a windowing component. The windowing component may set a first voltage level as an upper bound for a voltage window and set a second voltage level as a lower bound for the voltage window. The windowing component may modulate an input signal to have a maximum magnitude less than the upper bound for the voltage window and a minimum magnitude greater than the lower bound for the voltage window.