In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (S.sub.IN) at an input node (102) and outputs a corresponding time-encoded signal (S.sub.OUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (S.sub.IN) to the feedback signal (S.sub.FB) with hysteresis. This provides a pulse-width modulated output signal (S.sub.OUT) where the duty cycle encodes the input signal (S.sub.IN).

An electrical circuit for conditioning an analog electrical input signal into an analog electrical output signal includes a threshold circuit. The threshold circuit is configured to set a value of a conditioning parameter, under control of the analog electrical input signal and based on an electrical threshold. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal being below the electrical threshold, a first value. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal exceeding the electrical threshold, a second value different from the first value.

A device for integrating an electric current during a period T.sub.int, including an operational amplifier and a capacitor connected between a first input and an output of the amplifier, a second input of the amplifier being taken to a voltage VBUS, output voltage V.sub.out of the amplifier being saturated at a high voltage V.sub.satH and a low voltage V.sub.satH according to the charge quantity in the capacitor. The device also includes: a circuit for switching the terminals of the capacitor; and a circuit for triggering the circuit at least once during period T.sub.int when voltage V.sub.out both grows and is substantially equal to a reference voltage VREF, the voltage VREF being smaller than or equal to voltage V.sub.satH, and reference voltage VREF and voltage VBUS being selected to comply with relation 2.Math.VBUS?VREF?V.sub.satL; and a storage circuit for storing the number of triggerings having occurred between the initial time and the end time of the integration period.

A system and method for digitizing data from an imaging system includes sampling a signal from an optical detector with a first circuit having a first attenuation and with a second circuit having a second attenuation different than the first attenuation. The system and method further includes digitizing the sampled signal at a predetermined number of bits desired for an analog to digital conversion of the sampled signal by allocating a first portion of bits to digitizing a signal from the first circuit and allocating a second portion of bits to digitizing a signal from the second circuit. The system and method further includes encoding the first and second portion of bits into one monotonic digital word corresponding to a range of the sampled signal.

An AD converter includes a first DAC circuit, a second DAC circuit, a comparison circuit, a control circuit, and a control switch. The comparison circuit is connected to a first output node of the first DAC circuit and a second output node of the second DAC circuit and compares an electric potential of the first output node with an electric potential of the second output node. The control circuit controls the first DAC circuit and the second DAC circuit in accordance with a result of the comparison acquired by the comparison circuit. The control switch controls turning on and off of connection between a first input node of the first DAC circuit and a second input node of the second DAC circuit.

Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage; nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (S.sub.IN) at an input node (102) and outputs a corresponding time-encoded signal (S.sub.OUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (S.sub.IN) to the feedback signal (S.sub.FB) with hysteresis. This provides a pulse-width modulated output signal (S.sub.OUT) where the duty cycle encodes the input signal (S.sub.IN).

An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer?2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

An image sensing apparatus comprises: a pixel unit; a generator that generates and outputs a plurality of reference signals having different slopes from each other that increase in proportion to elapsation of time; a selector that selects one of the plurality of reference signals; and an analog-to-digital converter that converts an analog signal outputted from the pixel unit of an image sensor to a digital signal using the reference signal selected by the selector, wherein the generator generates the plurality of reference signals in parallel, and in a case where an analog signal of a reset level is outputted from the pixel unit, the selector changes the reference signal selected from the plurality of reference signals each time the selected reference signal exceeds the analog signal.