An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

A motor drive system includes a MUX circuit, a DC voltage scaling circuit, a fault detection circuit, an ADC, and an FPGA. The MUX circuit selectively establishes a MUX input signal path and a MUX output signal path. The DC voltage scaling circuit measures a DC link voltage. The fault detection circuit receives the output DC link voltage and outputs one of a normal operation signal or a fault signal in response to comparing the DC link voltage to one or both of a U/V reference voltage and an O/V reference voltage. The ADC converts one or more input analog voltages into respective corresponding output digital voltages. The FPGA is in signal communication with the ADC output (ADC.sub.OUT) and the MUX circuit, and is configured to control the motor drive system based on a comparison between one or more of the output digital voltages.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

A method for amplifying an echo signal, in which an analog echo signal suitable for detection of a vehicle's surroundings is amplified by a gain dependent on the transit time of the echo signal, the analog echo signal being amplified by an amplifier having a plurality of outputs, each having a different gain, and a downstream A/D converter having a time-variable reference voltage. In the process, there is a switch between the different outputs of the amplifier at predefined switching points in time, and the reference voltage of the A/D converter varies over time between the switching points in time in such a way that the echo signal is present at the output of the A/D converter with a transit time-dependent total gain having a predefined characteristic.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

To provide a measuring device wherein a measurement range corresponding to a wave shape to be measured can be set with a simple configuration. A measuring device (100) has: a measuring unit that measures changes of indexes with time, said indexes relating to an object event; a conversion unit that converts a measurement value measured by means of the measuring unit into a predetermined format within a previously set measurement range; and a control unit that controls the measurement range. The control unit changes the measurement range in the cases where a conversion value obtained by converting the measurement value by means of the conversion unit satisfies predetermined conditions in a predetermined period.

A device for integrating an electric current during a period T.sub.int, including an operational amplifier and a capacitor connected between a first input and an output of the amplifier, a second input of the amplifier being taken to a voltage VBUS, output voltage V.sub.out of the amplifier being saturated at a high voltage V.sub.satH and a low voltage V.sub.satH according to the charge quantity in the capacitor. The device also includes: a circuit for switching the terminals of the capacitor; and a circuit for triggering the circuit at least once during period T.sub.int when voltage V.sub.out both grows and is substantially equal to a reference voltage VREF, the voltage VREF being smaller than or equal to voltage V.sub.satH, and reference voltage VREF and voltage VBUS being selected to comply with relation 2.Math.VBUSVREFV.sub.satL; and a storage circuit for storing the number of triggerings having occurred between the initial time and the end time of the integration period.

The disclosed high-performance time-to-digital converter (TDC) incorporates ratiometric signal quantization with correlated double sampling (CDS). The TDC includes an input voltage circuit that outputs an input voltage signal and a fractional reference voltage circuit that outputs a fractional reference voltage signal. The TDC also includes a quantizer circuit that provides a differential output of the input voltage signal and the fractional reference voltage signal as a digital time value. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.