A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.

An electrical circuit for conditioning an analog electrical input signal into an analog electrical output signal includes a threshold circuit. The threshold circuit is configured to set a value of a conditioning parameter, under control of the analog electrical input signal and based on an electrical threshold. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal being below the electrical threshold, a first value. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal exceeding the electrical threshold, a second value different from the first value.