An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

The present disclosure relates to a signal processing apparatus and method, an imaging element, and an electronic apparatus capable of suppressing an increase in area. The present disclosure divides a predetermined current generated by receiving a gain control signal that controls a gain into a plurality of output currents and a non-output current in accordance with a value of an input digital signal and outputs the plurality of output currents as a plurality of analog signals. The present technology can be applied to for example, electronic circuits such as a D/A converter circuit and an A/D converter circuit, imaging elements such as a CMOS image sensor, electronic apparatuses such as a digital still camera, and the like.

An analog signal processing module includes a processor and a comparator circuit module having a comparator circuit input and a comparator circuit output, the comparator circuit module being configured to receive a first analog signal at the comparator circuit input and generate a digital output, wherein the comparator circuit output is connected to the processor. A digital-to-analog converter (DAC) module is configured to receive a digital output from the processor and convert the digital output to a second analog signal. An operational amplifier (OpAmp) circuit module has an OpAmp circuit input and an OpAmp circuit output, the OpAmp circuit module being configured to receive the second analog signal at the OpAMp circuit input. A feedback loop is formed by the processor, the DAC module, and the OpAMp circuit module, and is configured to implement an amplification function or attenuation function performed by the OpAmp circuit module.

A radio frequency front-end (RF-FE) device with a reconfigurable common-mode feedback control. The device includes a plurality of RF-FE channels and a reconfiguration switch. An RF-FE channel includes a common-mode feedback loop. The common-mode feedback loop is configured to detect a common-mode signal in differential signals in the RF-FE channel and generate a feedback signal to set the common-mode signal. The reconfiguration switch is configured to couple common-mode feedback loops of two or more RF-FE channels based on an operation mode. The reconfiguration switch may be controlled to couple common-mode feedback loops of two or more RF-FE channels if the two or more RF-FE channels receive a same input signal and decouple common-mode feedback loops of two or more RF-FE channels if the two or more RF-FE channels receive different input signals.

Disclosed is a sound recording circuit capable of adjusting microphone sensitivity and preventing sound cracks caused by overly loud sound. The sound recording circuit includes: a microphone bias circuit configured to provide a bias voltage for a microphone circuit; an AC coupling capacitor configured to output an analog input signal according to a microphone signal of the microphone circuit; an analog amplifier circuit configured to output an analog output signal according to the analog input signal; an analog-to-digital converter configured to output a digital input signal according to the analog output signal; a digital amplifier circuit configured to output a digital output signal according to the digital input signal; and a signal detector configured to control an analog gain of the analog amplifier circuit, a digital gain of the digital amplifier circuit, and the bias voltage of the microphone bias circuit.

An analog signal processing module includes a processor and a comparator circuit module having a comparator circuit input and a comparator circuit output, the comparator circuit module being configured to receive a first analog signal at the comparator circuit input and generate a digital output, wherein the comparator circuit output is connected to the processor. A digital-to-analog converter (DAC) module is configured to receive a digital output from the processor and convert the digital output to a second analog signal. An operational amplifier (OpAmp) circuit module has an OpAmp circuit input and an OpAmp circuit output, the OpAmp circuit module being configured to receive the second analog signal at the OpAMp circuit input. A feedback loop is formed by the processor, the DAC module, and the OpAMp circuit module, and is configured to implement an amplification function or attenuation function performed by the OpAmp circuit module.

A digital to analog converter (DAC) can include a current mode DAC to receive an OC word from digital logic indicating an amount of current to add to or remove from sources of respective transistors of an amplifier and generate a current based on the OC word, an active output stage including a positive current mirror and a negative current mirror to generate a positive current and a negative current based on at least a portion of the generated current, and a plurality of outputs including a plurality of sink outputs and a plurality of source outputs to provide the positive and negative currents to the sources of the respective transistors.

A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.