The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.

A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.

A sum-of-products calculation apparatus is provided. The sum-of-products calculation apparatus includes an analog-to-digital (A-to-D) conversion circuit having an encoder circuit and a plurality of inverters. Threshold voltages of the inverters are set according to classification threshold values of an activation function. The inverters generate a plurality of bit signals in response to an analog sum-of-products signal. The encoder circuit encodes the bit signals to generate a digital signal.

An apparatus and method is disclosed with embodiments of a: 1. digital to analog and reference time converter; 2. analog and reference time to digital converter; 3. Sheahan non-linear time-varying, analog and digital control system; and 4. Sheahan Communication Channel are described in detail herein. Some embodiments use time stamp having 72 bits of time data sufficient to identify each clock pulse of a 9.192631770 GHz clock signal plus an additional 8 bits representing 2.sup.8=256 interpolated clock phases in order reach a resolution of approximately 0.425 picoseconds per clock phase. Thus an 80 bit time stamp is generated and used as described herein.

Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.

An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that. of a least significant. bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.