A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.

A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

A control circuit and a method of calibrating a signal converter (such as DAC) are disclosed. The control circuit can be an existing control circuit, so no additional calibration circuit is required and the circuit area can be reduced. The control circuit can be an embedded microcontroller or other type of microcontroller. In general, the microcontroller includes an analog comparator and an arithmetic unit. With the combination of using the arithmetic unit to execute firmware program codes and using of the analog comparator, the control circuit is able to calibrate the signal converter.

An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

A system and method of converting an analog input signal to a digital output signal includes coupling an analog input signal to a plurality of analog-to-digital converters (ADCs) arranged in a parallel configuration. Pseudo-random discrete valued complementary offset voltage levels that span an input voltage range of the sum of the plurality of ADCs are generated. An amount of continuous, analog dither that randomly varies at values between the discrete offset voltage levels is generated, the analog dither being less than steps between the discrete offset voltage levels. On different clock cycles, different discrete offset voltage levels are coupled to at least some of the ADCs. At each ADC, the respectively coupled analog input, discrete offset voltage level, and continuous analog dither are quantized to obtain a digital output. The respective digital outputs are combined to obtain a linearized digital representation of the analog input signal.

The present invention discloses an analog-to-digital conversion circuit having remained time measuring mechanism is provided. A digital-to-analog conversion (DAC) circuit samples input voltages to generate output voltages. A comparator compares the output voltages to generate a comparison result. A control circuit switches a configuration of the DAC circuit by using a digital code according to the comparison result. A comparison determining circuit sets a stage indication signal at a finished state after the comparison result is generated. A comparison stage counting circuit accumulates a termination number according to the stage indication signal to set a conversion indication signal at the finished state when the termination number reaches a predetermined number. A time accumulating circuit starts to accumulate a remained time when the conversion indication signal is at the finished state and finishes accumulation when a sampling indication signal is at a sampling state.

A quantizer including passive summers, dynamic comparators and a clock generator. Each passive summer samples the input voltages and a reference voltage scaled by one of multiple graduated gains, and subtracts the scaled reference voltage from the sum of the input voltages. The graduated gains divide a predetermined voltage range into multiple voltage subranges, each between sequential pairs of the passive summers. The dynamic comparators compare each sequential pair of passive summer output voltages according to multiple splitting ratios and provide corresponding quantization bits. The dynamic comparators are activated in groups to reduce comparator kickback. Each dynamic comparator recharges the passive summer output voltages coupled to its inputs back to their initial voltage values to reduce kickback residual. The passive summers eliminate the need for a resistor string to generate the reference voltages. Staggered activation and comparator recharging replace preamplifiers used to suppress kickback and kickback residuals.

An analog-to-digital converter includes a comparator configured to compare an input voltage and a conversion voltage and to generate a comparison result; a digital-to-analog converter configured to generate the conversion voltage according to a digital output signal; and a control circuit including a conversion control circuit configured to determine the digital output signal corresponding to the input voltage based on the comparison result; and a correction control circuit configured to correct an error of the digital output signal by increasing or decreasing the digital output signal based on the comparison result after the digital output signal is determined.