The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of on and off transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.

Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.

The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of on and off transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.

An analog-to-digital converter is provided which is configured to output an n-bit signal in response to an analog input signal. n is greater than 1. The converter comprises n comparators, where each comparator is configured to output one bit of the n-bit signal and comprising a first input and a second input. A first comparator is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal. For the remaining comparators, an i-th comparator, i=2 . . . n, is configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device. The i-th input device is configured to selectively provide one of 2.sup.i1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

An analog-to-digital converter includes a comparator configured to compare an input voltage and a conversion voltage and to generate a comparison result; a digital-to-analog converter configured to generate the conversion voltage according to a digital output signal; and a control circuit including a conversion control circuit configured to determine the digital output signal corresponding to the input voltage based on the comparison result; and a correction control circuit configured to correct an error of the digital output signal by increasing or decreasing the digital output signal based on the comparison result after the digital output signal is determined.

A circuit includes at least one coupling node configured to be coupled, via a cable, to a load to transmit a supply voltage thereto. The circuit includes test circuitry configured to sense at least one sensing signal indicative of a value of the cable impedance and/or of the cable voltage across the cable, to perform a comparison between the at least one sensing signal and at least one threshold indicative either of a threshold resistance value for the cable impedance or indicative of a threshold voltage value for the cable voltage, produce a comparison signal as a result of the comparison.