A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

A converter includes a switched capacitor circuit that includes at least one capacitor and a plurality of main switches to provide an output current in response to an input voltage applied to the switched capacitor circuit. The converter further includes one or more bypass transistor switches to selectively provide an additional output current. The converter includes a common controller that controls the plurality of main switches and the one or more bypass transistor switches.

Errors in a cyclic analog to digital converter are reduced. An analog to digital converter is a cyclic analog to digital converter for converting an analog input signal into a digital output signal by performing a plurality of times of cycle processing on the analog input signal. A cycle processing unit performs the cycle processing and outputs a digital signal indicating a value of each bit of the digital output signal. An output circuit receives the digital signal output from the cycle processing unit and outputs, as an output signal, a signal obtained by inverting the digital signal every other cycle. A signal input to the cycle processing unit in second and subsequent cycles is generated in the cycle processing in a previous cycle. In the cycle processing, processing for inverting the signal input to the cycle processing is performed.

Errors in a cyclic analog to digital converter are reduced. An analog to digital converter is a cyclic analog to digital converter for converting an analog input signal into a digital output signal by performing a plurality of times of cycle processing on the analog input signal. A cycle processing unit performs the cycle processing and outputs a digital signal indicating a value of each bit of the digital output signal. An output circuit receives the digital signal output from the cycle processing unit and outputs, as an output signal, a signal obtained by inverting the digital signal every other cycle. A signal input to the cycle processing unit in second and subsequent cycles is generated in the cycle processing in a previous cycle. In the cycle processing, processing for inverting the signal input to the cycle processing is performed.

An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2.sup.(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2.sup.(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2.sup.(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2.sup.(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

A converter includes a switched capacitor circuit that includes at least one capacitor and a plurality of main switches to provide an output current in response to an input voltage applied to the switched capacitor circuit. The converter further includes one or more bypass transistor switches to selectively provide an additional output current. The converter includes a common controller that controls the plurality of main switches and the one or more bypass transistor switches.

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.