A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C.sub.n[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V.sub.d and the digital output port.

An analog-to-digital conversion device is provided for converting an input signal pair to generate an output signal. The analog-to-digital conversion device includes switch groups, capacitors, a comparator, and a controller. The switch groups receive the input signal pair and reference voltages, and selects to output one of the input signal pair and the reference voltages according to a control signal to generate selection voltages respectively. The capacitors receive the selection voltages respectively and generate a first comparison voltage and a second comparison voltage. The comparator compares the first comparison voltage and the second comparison voltage to generate a comparison result signal. The controller sets conversion times for converting bits of the output signal according to the comparison result signal, wherein at least two of the conversion times are different.

Provided is a successive approximation type analog/digital converter for generating a digital output signal corresponding to an analog input signal, including a capacitive digital/analog converter including a plurality of capacitors covering the most significant bit through the least significant bit, sampling an analog signal corresponding to the input signal, and generating an analog output signal corresponding to a digital input, a comparator performing successive approximation of the analog output signal for the most significant bit through the least significant bit with a comparison reference voltage, and a control circuit generating the digital input corresponding to a result of the successive approximation by the comparator and generating the digital output signal corresponding to the sampled analog signal corresponding to the result of the successive approximation by the comparator.

A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a common-mode reference voltage generation circuit uses one or more additional sampling switched capacitors to selectively couple the first and second reference voltages to the amplifier input during the gain phase when the input voltage is between the high and low threshold voltages using a switching configuration of switches that are controllable to connect the sampling switched capacitors to the one or more central nodes in the sampling phase, and to connect the amplifier output in feedback to the input sampling circuit in the gain phase while simultaneously connecting the one or more central nodes to the first amplifier input.

An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit configured to receive an analog input signal; a digital-to-analog converter (DAC); an adder having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit coupled to an output of the adder and configured to perform a comparison operation; and a control circuit, coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.

There is provided an integrator including: a first order delay unit which outputs an output signal obtained by delaying a signal in accordance with an input signal; a first feedback unit which generates a first feedback signal in accordance with the output signal; a second feedback unit which generates a second feedback signal in accordance with the output signal; an addition and subtraction unit which adds and subtracts the first feedback signal and the second feedback signal, respectively, to and from the input signal, for an input to the delay unit; and a control unit which causes the second feedback unit to operate as a delay circuit during the first period, and causes the second feedback unit to operate as a gain circuit having a gain smaller than 0 during the second period.

An example apparatus includes bias control circuitry and sampling circuitry. The example sampling circuitry includes a first switch coupled to a first capacitor in series between an input voltage terminal and a common mode voltage terminal, the first switch including a first terminal coupled to the input voltage terminal. Additionally, the example sampling circuitry includes a second switch coupled to a second capacitor in series between the input voltage terminal and the common mode voltage terminal, the second switch including a first terminal coupled to the input voltage terminal. The example sampling circuitry also includes a third switch including a first terminal, a second terminal, and a control terminal, the first terminal of the third switch coupled to a power supply terminal, the second terminal of the third switch coupled between the first switch and the first capacitor, the control terminal coupled to the bias control circuitry.