A circuit comprising: an analog-to-digital converter configured to generate a digital signal based on a received input voltage and a received reference voltage; a capacitor array; and a switching network configured to switch each capacitor of the capacitor array between a first conductor connected to a supply voltage source, and a second conductor connected to the reference voltage; wherein the analog-to-digital converter comprises a logic configured to control the switching network to selectively switch between the first conductor and the second conductor based on the generated digital signal.

A switched capacitor circuit, including a metal-oxide-semiconductor field-effect transistor-based switch comprising: a first metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to a first node and the drain is connected to a second node or wherein the drain is connected to the first node and the source is connected to the second node; a second metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to the drain and the source and the drain are together connected to the second node; a first capacitor connected between the first node and a third node; and a second capacitor connected between the second node and the third node.

A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.

The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch S.sub.M to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array C.sub.A including a binary array of P-bit unit capacitors, a calibration structure C.sub.fraq, and a ground switch S.sub.k. The calibration structure C.sub.fraq includes four unit capacitors and two switches S.sub.1 and S.sub.2. By controlling the switches S.sub.1 and S.sub.2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.

A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

A circuit comprises a plurality of bit lines, a global counter configured to provide a count value, a global reference source, a plurality of capacitors, a comparator, a storage element, and capacitor selector circuitry. The capacitor selector circuitry is configured to select, in dependence on the count value, one or more capacitors from the plurality of capacitors, and wherein the selection of the one or more capacitors is further in dependence on pre-coded codes receivable from an agent separate from the circuit, the pre-coded codes enabling specifying respective first and second sets of the plurality of capacitors as respective one or more capacitors having respective first and second capacitance values, the pre-coded codes further enabling specifying selection of the first set to be performed at an earlier time than selection of the second set, and the second capacitance value is more than the first capacitance value