An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.

This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.

An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.

An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.

A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance.

This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.

This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.