An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, V.sub.IN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.

Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period. The second integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the second integration polarity switching signal in the first integration period.

A digital unit cell, readout circuit for a digital unit cell and a method of operating an analog counter of a digital unit cell is disclosed. The readout circuit includes storage capacitor for storing a voltage remaining at an analog counter at the end of an integration period, and a comparator circuit. The comparator circuit compares a dummy voltage provided from the analog counter during a readout period to the voltage at the storage capacitor, and determines the voltage at the storage capacitor when the dummy voltage falls below the voltage at the storage capacitor.

A detector for measuring a resistance of a variable resistance sensor (VRS) that varies with respect to a time-varying stimulus (e.g., temperature) includes a voltage reference having variation with respect to operating conditions and a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector. The sensed voltage includes error due to the variation of the voltage reference. The detector also includes a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an ADC that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance. The PGA is non-varying with respect to the time-varying stimulus.

A method includes selecting at least one first voltage that defines subsets of DC voltages from among an ordered set of DC voltages, comparing the first voltage with a DC reference voltage, selecting one of the subsets based on a result of the comparing, and comparing each voltage of the selected subset with the reference voltage.

A device having a capacitive sampling structure that allows for removal of sampling noise can be implemented in a variety of applications. Noise cancellation can be achieved by storing on an auto-zero capacitor a scaled replica of kT/C noise by a mechanism of correlated sampling. In an example embodiment, a set of switches can be arranged such that, in switching, scaled thermal noise, generated in an acquisition phase in which a voltage signal is input to an input capacitor structure, is captured on an output capacitor structure and, in a conversion phase, the captured thermal noise is cancelled or compensated from an output of the output capacitor structure.

Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.

A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.