The application discloses a time-to-digital conversion circuit (100) including a first oscillator (110), a second oscillator (120), a first counting circuit (130), a second counting circuit (140), a first conversion circuit (150) and a processing circuit (160). The first oscillator is activated by a first signal and includes oscillating units having a first delay amount, wherein the first counting circuit is configured to count a number of times that the first tail end output signal of the first oscillator changes and store the same as a first counting result; the second counting circuit counts a number of oscillating units with an output change, other than the first tail end oscillating unit and stores the same as a second counting result; the first conversion circuit generates a first conversion signal according to the first counting result and the second counting result; the processing circuit generates the output signal at least according to the first conversion signal.

This invention relates to multichannel signal processing systems using synchronous protocols I2S (Inter-IC Sound Bus) and SPI (Serial Peripheral Bus) for sequenced data exchange, and providing unified synchronization of processed data. The system and method for synchronously multiplexing data streams in the I2S or SPI formats involves transformation of a standard Left/Right Clock (LRCK) sampled pulse signal of the I2S format or a Chip Select (CS) pulse signal of the SPI format into a LRCLt signal comprising a time stamp code and start and end marker codes of the synchronization clock signal, LRCK or CS, respectively. The presence of the marker codes and the time stamp code enables to restore the pulse signal, LRCK or CS, respectively, in the process of data stream program processing and link each discrete sample to the time stamp. The digital stream multiplexing system includes m channel groups for collection of synchronous data in the I2S or SPI synchronous protocol, a clock generator, a host processor and a means of transforming the LRCK or CS signal into the LRCKt signal. The technical effect consists in removal of limitations on a number of fully synchronized data streams in the I2S or SPI formats and, at the same time, simplification of the synchronization system and method and reduction in requirements to hardware resources.

This application relates an activity detector (100) for detecting signal activity in an input audio signal (S.sub.IN), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator (201) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM (103) having a second hysteretic comparator (401) is arranged to receive a reference voltage (V.sub.MID) and generate a clock signal (S.sub.CLK). A time-decoding converter (102) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor (104) is responsive to a count signal (S.sub.CT) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

This application relates an activity detector (100) for detecting signal activity in an input audio signal (S.sub.IN), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator (201) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM (103) having a second hysteretic comparator (401) is arranged to receive a reference voltage (V.sub.MID) and generate a clock signal (S.sub.CLK). A time-decoding converter (102) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor (104) is responsive to a count signal (S.sub.CT) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

The application discloses a time-to-digital conversion circuit (100) including a first oscillator (110), a second oscillator (120), a first counting circuit (130), a second counting circuit (140), a first conversion circuit (150) and a processing circuit (160). The first oscillator is activated by a first signal and includes oscillating units having a first delay amount, wherein the first counting circuit is configured to count a number of times that the first tail end output signal of the first oscillator changes and store the same as a first counting result; the second counting circuit counts a number of oscillating units with an output change, other than the first tail end oscillating unit and stores the same as a second counting result; the first conversion circuit generates a first conversion signal according to the first counting result and the second counting result; the processing circuit generates the output signal at least according to the first conversion signal.

A system may include a digital delta-sigma modulator configured to receive a digital audio input signal and quantize the digital audio input signal into a quantized signal, a filter configured to receive the quantized signal and perform filtering on the quantized signal to generate a filtered quantized signal, the filter having a variable group delay, and a current-mode digital-to-analog converter configured to receive the filtered quantized signal and convert the filtered quantized signal into an equivalent current-mode analog audio signal.

This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (S.sub.IN) and outputs a time encoded signal (S.sub.PWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronise any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (S.sub.OUT) from the modulator are thus synchronised to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronised to the first clock signal.

This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (S.sub.IN) and outputs a time encoded signal (S.sub.PWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronise any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (S.sub.OUT) from the modulator are thus synchronised to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronised to the first clock signal.

An electrical circuit can bias a sensor, measure current from a sensor, or both of these. In some examples, the electrical circuit can include a comparator having two input terminals and an output terminal. The comparator can be configured to compare input signals applied to the two input terminals and generate an output signal at the output terminal based on the comparison. The electrical circuit can include a switch having a control terminal that is electrically coupled to the output terminal of the comparator. The switch can also include a first connection terminal that is electrically coupled to the sensor and a second connection terminal that is electrically coupled to a charge-packet source. The switch can be switchable between (i) an open state to electrically decouple the sensor from the charge-packet source, and (ii) a closed state to electrically couple the sensor to the charge-packet source.