This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (S.sub.C1, S.sub.C2) respectively, and generate respective first and second PWM signals (S.sub.PWM1, S.sub.PWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (S.sub.C1) corresponds to a sum of a first and second input signals (S.sub.1, S.sub.2) and the second combined signal (S.sub.C2) corresponds to the difference between the first and second input signals (S.sub.1, S.sub.2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D.sub.1, D.sub.2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D.sub.1, D.sub.2) and provides an output signal (D.sub.OUT) based on this difference.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (701) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (S.sub.IN) and outputs a time encoded signal (S.sub.PWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronise any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (S.sub.OUT) from the modulator are thus synchronised to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronised to the first clock signal.

This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (S.sub.C1, S.sub.C2) respectively, and generate respective first and second PWM signals (S.sub.PWM1, S.sub.PWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (S.sub.C1) corresponds to a sum of a first and second input signals (S.sub.1, S.sub.2) and the second combined signal (S.sub.C2) corresponds to the difference between the first and second input signals (S.sub.1, S.sub.2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D.sub.1, D.sub.2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D.sub.1, D.sub.2) and provides an output signal (D.sub.OUT) based on this difference.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (S.sub.IN) and outputs a time encoded signal (S.sub.PWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronize any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (S.sub.OUT) from the modulator are thus synchronized to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronized to the first clock signal.

This application relates an activity detector (100) for detecting signal activity in an input audio signal (S.sub.IN), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator (201) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM (103) having a second hysteretic comparator (401) is arranged to receive a reference voltage (V.sub.MID) and generate a clock signal (S.sub.CLK). A time-decoding converter (102) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor (104) is responsive to a count signal (S.sub.CT) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

This application relates to analog-to-digital converter (ADC) circuitry (200). A time-encoding modulator (TEM 201) has a comparator (104) and a loop filter (105) configured to generate a pulse-width-modulated (PWM) signal (S.sub.PWM) in response to an input signal (S.sub.IN) and a feedback signal (S.sub.FB). A controlled oscillator, such as a VCO (202) receives the PWM signal and generates an output oscillation signal (S.sub.OSC) with a frequency that varies based on a drive signal at a drive node (109), e.g. a drive node of a ring oscillator (107). The controlled oscillator (202) comprises at least one control switch (112) controlled by a switch control signal (S1) generated from the received PWM signal so as to control the drive strength of the drive signal applied to the drive node (109). The feedback signal (S.sub.FB) for the TEM (201) is derived from the controlled oscillator (202) so as to include any timing error between the PWM signal and the switch control signal (S1) applied to said control switch.

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (S.sub.IN) at an input node (102) and outputs a corresponding time-encoded signal (S.sub.OUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (S.sub.IN) to the feedback signal (S.sub.FB) with hysteresis. This provides a pulse-width modulated output signal (S.sub.OUT) where the duty cycle encodes the input signal (S.sub.IN).

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronized to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronized to the first clock signal (CLK.sub.1).