A digital-to-analog converter includes a core circuit including a plurality of input terminals for multi-bit digital signals, an output terminal for an analog signal, a plurality of constant current sources, a plurality of switch circuits connected in series to respective constant current sources of the plurality of constant current sources, and a load resistor connected to the output terminal. The core circuit being configured to select whether or not to allow a current to flow through each of the plurality of switch circuits based on the multi-bit digital signals and output a voltage generated by allowing the current flowing through each of the plurality of switch circuits to flow through the load resistor from the output terminal as an analog signal.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

An implantable pulse generator (IPG) is disclosed having an improved ability to steer anodic and cathodic currents between the IPG's electrodes. Each electrode node has at least one PDAC/NDAC pair to source/sink or sink/source a stimulation current to an associated electrode node. Each PDAC and NDAC receives a current with a magnitude indicative of a total anodic and cathodic current, and data indicative of a percentage of that total that each PDAC and NDAC will produce in the patient's tissue at any given time, which activates a number of branches in each PDAC or NDAC. Each PDAC and NDAC may also receive one or more resolution control signals specifying an increment by which the stimulation current may be adjusted at each electrode. The current received by each PDAC and NDAC is generated by a master DAC, and is preferably distributed to the PDACs and NDACs by distribution circuitry.

An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.

An implantable pulse generator (IPG) is disclosed having an improved ability to steer anodic and cathodic currents between the IPG's electrodes. Each electrode node has at least one PDAC/NDAC pair to source/sink or sink/source a stimulation current to an associated electrode node. Each PDAC and NDAC receives a current with a magnitude indicative of a total anodic and cathodic current, and data indicative of a percentage of that total that each PDAC and NDAC will produce in the patient's tissue at any given time, which activates a number of branches in each PDAC or NDAC. Each PDAC and NDAC may also receive one or more resolution control signals specifying an increment by which the stimulation current may be adjusted at each electrode. The current received by each PDAC and NDAC is generated by a master DAC, and is preferably distributed to the PDACs and NDACs by distribution circuitry.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (I.sub.D1, I.sub.D2, . . . I.sub.Dj) based on a respective input data value (D.sub.1, D.sub.2, . . . D.sub.j). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.

A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3.sup.rd-order and 5.sup.th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3.sup.rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.