The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2.sup.N1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.

A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3.sup.rd-order and 5.sup.th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3.sup.rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.

A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.

Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Digital-to-analog converter (master DAC) circuitry is disclosed that is programmable to set a controlled slew rate for pulses that are otherwise defined as having sharp amplitude transitions. For example, when producing a biphasic pulse, the constant amplitude and duration of first and second pulses phases can be defined and provided to the DAC in traditional fashion. Slew rate control signals control a slew rate DAC within the master DAC, which prescribes a slew rate that will appear at sharp transitions of the defined biphasic pulses, i.e., at the beginning of the first phase, at the transition from the first to the second phase, and at the end of the second phase. The slew rate can vary with the duration or frequency of the pulses, with lower slew rates used with longer durations and/or lower frequencies, and with higher slew rates used with shorter durations and/or higher frequencies.

An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.